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MCP433X/435X
7/8-Bit Quad SPI Digital POT with Volatile Memory
Features
* Quad Resistor Network * Potentiometer or Rheostat Configuration Options * Resistor Network Resolution: - 7-bit: 128 Resistors (129 Taps) - 8-bit: 256 Resistors (257 Taps) * RAB Resistances Options of: - 5 k - 10 k - 50 k - 100 k * Zero Scale to Full Scale Wiper Operation * Low Wiper Resistance: 75 (typical) * Low Tempco: - Absolute (Rheostat): 50 ppm typical (0C to 70C) - Ratiometric (Potentiometer): 15 ppm typical * SPI Serial Interface (10 MHz, Modes 0,0 and 1,1): - High-Speed Read/Writes to wiper registers * Resistor Network Terminal Disconnect Feature via Terminal Control (TCON) Register * Reset Input Pin * Brown-out Reset Protection (1.5V typical) * Serial Interface Inactive Current (2.5 A typical) * High-Voltage Tolerant Digital Inputs: Up to 12.5V * Supports Split Rail Applications * Internal Weak Pull-up on all Digital Inputs * Wide Operating Voltage: - 2.7V to 5.5V - Device Characteristics Specified - 1.8V to 5.5V - Device Operation * Wide Bandwidth (-3 dB) Operation: - 2 MHz (typical) for 5.0 k device * Extended Temperature Range (-40C to +125C)
Package Types (Top View)
MCP43X1 Quad Potentiometers TSSOP
P3A P3W P3B CS SCK SDI VSS P1B P1W P1A
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
P2A P2W P2B VDD SDO RESET NC P0B P0W P0A
MCP43X1 Quad Potentiometers 4x4 QFN*
P3W P2W P2A P3A P2B 15 13 12 11 6 P1B 7 P1W 8 P1A 9 10 P0A P0W
20 19 18 17 16 P3B CS SCK SDI VSS 1 2 3 4 5 EP 21
VDD RESET NC P0B
14 SDO
MCP43X2 Quad Rheostat TSSOP
P3W P3B CS SCK SDI VSS P1B
1 2 3 4 5 6 7
14 13 12 11 10 9 8
P2W P2B VDD SDO P0B P0W P1W
* Includes Exposed Thermal Pad (EP); see Table 3-1.
2010 Microchip Technology Inc.
DS22242A-page 1
MCP433X/435X
Device Block Diagram
VDD VSS CS SCK SDI SDO RESET Memory (16x9) Wiper0 (V) Wiper1 (V) Wiper2 (V) Wiper3 (V) TCON0 TCON1 Power-up/ Brown-out Control SPI Serial Interface Module and Control Logic Resistor Network 0 (Pot 0) Wiper 0 and TCON0 Register P0A P0W
P0B P1A P1W
Resistor Network 1 (Pot 1) Wiper 1 and TCON0 Register
P1B P2A P2W
Resistor Network 2 (Pot 2) Wiper 2 and TCON1 Register
P2B P3A P3W
Resistor Network 3 (Pot 3) Wiper 3 and TCON1 Register
P3B
Device Features
WiperLock Technology POR Wiper Setting # of POTs Control Interface # of Taps Memory Type Resistance (typical) RAB Options (k) Wiper - RW () 75 75 75 75 75 75 75 75 Wiper Configuration VDD Operating Range (2)
Device
MCP4331 MCP4332 MCP4341 MCP4342 MCP4351 MCP4352 MCP4361 MCP4362 Note 1: 2:
4 Potentiometer (1) SPI 4 Rheostat 4 Rheostat 4 Potentiometer (1) 4 Rheostat 4 Rheostat SPI SPI SPI SPI SPI 4 Potentiometer (1) SPI
RAM RAM EE EE RAM RAM EE EE
No No Yes Yes No No Yes Yes
Mid-Scale 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0
129 1.8V to 5.5V 129 1.8V to 5.5V 129 2.7V to 5.5V 129 2.7V to 5.5V 257 1.8V to 5.5V 257 1.8V to 5.5V 257 2.7V to 5.5V 257 2.7V to 5.5V
4 Potentiometer (1) SPI
Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor). Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted.
DS22242A-page 2
2010 Microchip Technology Inc.
MCP433X/435X
1.0 ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
Voltage on VDD with respect to VSS ..... -0.6V to +7.0V Voltage on CS, SCK, SDI, SDI/SDO, and RESET with respect to VSS ..................... -0.6V to 12.5V Voltage on all other pins (PxA, PxW, PxB and SDO) with respect to VSS ............... -0.3V to VDD + 0.3V Input clamp current, IIK (VI < 0, VI > VDD, VI > VPP ON HV pins) ........... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ....................................... 20 mA Maximum output current sunk by any Output pin ........................................................................... 25 mA Maximum output current sourced by any Output pin ........................................................................... 25 mA Maximum current out of VSS pin ...................... 100 mA Maximum current into VDD pin ......................... 100 mA Maximum current into PXA, PXW and PXB pins 2.5 mA Storage temperature ........... -65C to +150C Ambient temperature with power applied .......................................................... -40C to +125C Package power dissipation (TA = +50C, TJ = +150C) TSSOP-14 ......... 1000 mW TSSOP-20......................................................1110 mW QFN-20 (4x4) ................................................ 2320 mW Soldering temperature of leads (10 seconds) .................................................... +300C ESD protection on all pins 4 kV (HBM), ................................................................ 300V (MM) Maximum Junction Temperature (TJ) .............. +150C
2010 Microchip Technology Inc.
DS22242A-page 3
MCP433X/435X
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym VDD VHV Min 2.7 1.8 CS, SDI, SDO, SCK, RESET pin Voltage Range VDD Start Voltage to ensure Wiper Reset VDD Rise Rate to ensure Power-on Reset Delay after device exits the Reset state (VDD > VBOR) Supply Current (Note 10) VSS VSS VBOR -- Typ -- -- -- -- -- Max 5.5 2.7 12.5V VDD + 8.0V 1.65 Units V V V V V Serial Interface only. VDD 4.5V The CS pin will be at one VDD < 4.5V of three input levels (VIL, VIH or VIHH). (Note 6) RAM retention voltage (VRAM) < VBOR Conditions
Parameters Supply Voltage
VDDRR
(Note 9)
V/ms
TBORD
--
10
20
s
IDD
--
--
450
A
Serial Interface Active, VDD = 5.5V, CS = VIL, SCK @ 5 MHz, write all 0's to volatile Wiper 0 (address 0h) Serial Interface Inactive, CS = VIH, VDD = 5.5V Serial Interface Active, VDD = 5.5V, CS = VIHH, SCK @ 5 MHz, decrement volatile Wiper 0 (address 0h)
-- --
2.5 0.55
5 1
A mA
Note 1: 2: 3: 4: 5: 6: 7:
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP43X1 only. MCP43X2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network.
DS22242A-page 4
2010 Microchip Technology Inc.
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym RAB Min 4.0 8.0 40.0 80.0 Resolution Step Resistance N RS -- -- Nominal Resistance Match (| RABWC RABMEAN |)/ RABMEAN -- -- -- -- (| RBWWC RBWMEAN |)/ RBWMEAN -- -- -- -- Wiper Resistance (Note 3, Note 4) Nominal Resistance Tempco Ratiometeric Tempco Resistance Tracking Note 1: 2: 3: 4: 5: 6: 7: RW RAB/T -- -- -- -- -- VWB/T RTRACK -- Typ 5 10 50 100 257 129 RAB/ (256) RAB/ (128) 0.2 0.2 0.2 0.2 0.25 0.25 0.25 0.25 75 75 50 100 150 15 Section 2.0 -- -- 1.50 1.25 1.0 1.0 1.75 1.50 1.25 1.25 160 300 -- -- -- -- Max 6.0 12.0 60.0 120.0 Units k k k k Taps Taps % % % % % % % % Conditions -502 devices(Note 1) -103 devices(Note 1) -503 devices(Note 1) -104 devices(Note 1) 8-bit 7-bit 8-bit 7-bit 5 k 10 k 50 k 100 k 5 k 10 k 50 k 100 k VDD = 5.5 V, IW = 2.0 mA, code = 00h VDD = 2.7 V, IW = 2.0 mA, code = 00h Code = Full Scale No Missing Codes No Missing Codes Note 6 Note 6 MCP43X1 devices only
Parameters Resistance ( 20%)
ppm/C TA = -20C to +70C ppm/C TA = -40C to +85C ppm/C TA = -40C to +125C ppm/C Code = Mid-scale (80h or 40h) ppm/C See Section 2.0 "Typical Performance Curves"
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP43X1 only. MCP43X2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network.
2010 Microchip Technology Inc.
DS22242A-page 5
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym VA,VW,VB Min Vss Typ -- Max VDD Units V Conditions Note 5, Note 6
Parameters Resistor Terminal Input Voltage Range (Terminals A, B and W) Maximum current through A, W or B Leakage current into A, W or B Note 1: 2: 3: 4: 5: 6: 7:
IW
--
--
2.5
mA
Worst case current through wiper when wiper is either Full Scale or Zero Scale. (Note 6) MCP43X1 PxA = PxW = PxB = VSS MCP43X2 PxB = PxW = VSS
IWL
-- --
100 100
-- --
nA nA
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP43X1 only. MCP43X2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network.
DS22242A-page 6
2010 Microchip Technology Inc.
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym VWFSE Min -6.0 -4.0 -3.5 -2.0 -0.8 -0.5 -0.5 -0.5 Zero Scale Error (MCP43X1 only) (8-bit code = 00h, 7-bit code = 00h) VWZSE -- -- -- -- -- -- -- -- Potentiometer Integral Non-linearity Potentiometer Differential Non-linearity Bandwidth -3 dB (See Figure 2-92, load = 30 pF) INL -1 -0.5 DNL -0.5 -0.25 BW -- -- -- -- -- -- -- -- Note 1: 2: 3: 4: 5: 6: 7: Typ -0.1 -0.1 -0.1 -0.1 -0.1 -0.1 -0.1 -0.1 +0.1 +0.1 +0.1 +0.1 +0.1 +0.1 +0.1 +0.1 0.5 0.25 0.25 0.125 2 2 1 1 200 200 100 100 Max -- -- -- -- -- -- -- -- +6.0 +3.0 +3.5 +2.0 +0.8 +0.5 +0.5 +0.5 +1 +0.5 +0.5 +0.25 -- -- -- -- -- -- -- -- Units LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb MHz MHz MHz MHz kHz kHz kHz kHz 100 k 50 k 10 k 8-bit 7-bit 8-bit 7-bit 5 k 100 k 50 k 10 k 5 k 100 k 50 k 10 k 5 k Conditions 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V
Parameters Full Scale Error (MCP43X1 only) (8-bit code = 100h, 7-bit code = 80h)
3.0V VDD 5.5V MCP43X1 devices only (Note 2) 3.0V VDD 5.5V MCP43X1 devices only (Note 2) 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit Code = 80h Code = 40h Code = 80h Code = 40h Code = 80h Code = 40h Code = 80h Code = 40h
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP43X1 only. MCP43X2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network.
2010 Microchip Technology Inc.
DS22242A-page 7
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym R-INL Min -1.5 -8.25 Typ 0.5 +4.5 Max +1.5 +8.25 Units LSb LSb 5 k Conditions 8-bit 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 1.8V, IW = 190 A LSb LSb 7-bit 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 1.8V, IW = 190 A LSb LSb 10 k 8-bit 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 1.8V, IW = 150 A LSb LSb 7-bit 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 1.8V, IW = 150 A LSb LSb 50 k 8-bit 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 1.8V, IW = 30 A LSb LSb 7-bit 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 1.8V, IW = 30 A LSb LSb 100 k 8-bit 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7) 1.8V, IW = 15 A LSb LSb 7-bit 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7) 1.8V, IW = 15 A
Parameters Rheostat Integral Non-linearity MCP43X1 (Note 4, Note 8) MCP43X2 devices only (Note 4)
Section 2.0 -1.125 -6.0 0.5 +4.5 +1.125 +6.0
Section 2.0 -1.5 -5.5 0.5 +2.5 +1.5 +5.5
Section 2.0 -1.125 -4.0 0.5 +2.5 +1.125 +4.0
Section 2.0 -1.5 -2.0 0.5 +1 +1.5 +2.0
Section 2.0 -1.125 -1.5 0.5 +1 +1.125 +1.5
Section 2.0 -1.0 -1.5 0.5 +0.25 +1.0 +1.5
Section 2.0 -0.8 -1.125 0.5 +0.25 +0.8 +1.125
Section 2.0 Note 1: 2: 3: 4: 5: 6: 7:
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP43X1 only. MCP43X2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network.
2010 Microchip Technology Inc.
DS22242A-page 8
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym R-DNL Min -0.5 -1.0 Typ 0.25 +0.5 Max +0.5 +1.0 Units LSb LSb 5 k Conditions 8-bit 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 1.8V, IW = 190 A LSb LSb 7-bit 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 1.8V, IW = 190 A LSb LSb 10 k 8-bit 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 1.8V, IW = 150 A LSb LSb 7-bit 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 1.8V, IW = 150 A LSb LSb 50 k 8-bit 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 1.8V, IW = 30 A LSb LSb 7-bit 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 1.8V, IW = 30 A LSb LSb 100 k 8-bit 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7) 1.8V, IW = 15 A LSb LSb 7-bit 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7) 1.8V, IW = 30 A
Parameters Rheostat Differential Non-linearity MCP43X1 (Note 4, Note 8) MCP43X2 devices only (Note 4)
Section 2.0 -0.375 -0.75 0.25 +0.5 +0.375 +0.75
Section 2.0 -0.5 -1.0 0.25 +0.25 +0.5 +1.0
Section 2.0 -0.375 -0.75 0.25 +0.5 +0.375 +0.75
Section 2.0 -0.5 -0.5 0.25 0.25 +0.5 +0.5
Section 2.0 -0.375 -0.375 0.25 0.25 +0.375 +0.375
Section 2.0 -0.5 -0.5 0.25 0.25 +0.5 +0.5
Section 2.0 -0.375 -0.375 0.25 0.25 +0.375 +0.375
Section 2.0 Note 1: 2: 3: 4: 5: 6: 7:
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP43X1 only. MCP43X2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network.
DS22242A-page 9
2010 Microchip Technology Inc.
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym CAW CW CBW VIH Min -- -- -- 0.45 VD
D
Parameters Capacitance (PA) Capacitance (Pw) Capacitance (PB) Schmitt Trigger High Input Threshold Schmitt Trigger Low Input Threshold Hysteresis of Schmitt Trigger Inputs High Voltage Input Entry Voltage High Voltage Input Exit Voltage High Voltage Limit Output Low Voltage (SDO) Output High Voltage (SDO) Note 1: 2: 3: 4: 5: 6: 7:
Typ 75 120 75 --
Max -- -- -- --
Units pF pF pF V
Conditions f =1 MHz, Code = Full Scale f =1 MHz, Code = Full Scale f =1 MHz, Code = Full Scale 2.7V VDD 5.5V (Allows 2.7V Digital VDD with 5V Analog VDD) 1.8V VDD 2.7V
Digital Inputs/Outputs (CS, SDI, SDO, SCK, WP, RESET)
0.5 VDD VIL --
-- --
-- 0.2VDD
V V
VHYS
--
0.1VDD
--
V
VIHH VIHH VMAX VOL VOH
8.5 -- -- VSS VSS 0.7VDD 0.7VDD
-- -- -- -- -- -- --
12.5 (6) VDD + 0.8V 12.5 (6) 0.3VDD 0.3VDD VDD VDD
V V V V V V V Pin can tolerate VMAX or less. IOL = 5 mA, VDD = 5.5V IOL = 1 mA, VDD = 1.8V IOH = -2.5 mA, VDD = 5.5V IOL = -1 mA, VDD = 1.8V
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP43X1 only. MCP43X2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network.
DS22242A-page 10
2010 Microchip Technology Inc.
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym IPU Min -- -- CS Pull-up/ Pull-down Resistance RESET Pull-up Resistance Input Leakage Current Pin Capacitance Value Range TCON POR/BOR Setting Wiper POR/BOR Setting Power Requirements Power Supply Sensitivity (MCP43X1) Note 1: 2: 3: 4: 5: 6: 7: PSS -- -- 0.0015 0.0015 0.0035 0.0035 %/% %/% 8-bit 7-bit VDD = 2.7V to 5.5V, VA = 2.7V, Code = 80h VDD = 2.7V to 5.5V, VA = 2.7V, Code = 40h N RCS -- Typ -- 170 16 Max 1.75 -- -- Units mA A k Conditions Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VCS = 12.5V CS pin, VDD = 5.5V, VCS = 3V VDD = 5.5V, VCS = 3V
Parameters Weak Pull-up Current
RRESET IIL CIN, COUT N
-- -1 -- 0h 0h
16 -- 10 -- -- 1FF 080h 040h
-- 1 -- 1FFh 1FFh
k A pF hex hex hex hex hex
VDD = 5.5V, VRESET = 0V VIN = VDD (all pins) and VIN = VSS (all pins except RESET) fC = 20 MHz 8-bit device 7-bit device All terminals connected 8-bit 7-bit
RAM (Wiper, TCON) Value
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP43X1 only. MCP43X2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network.
2010 Microchip Technology Inc.
DS22242A-page 11
MCP433X/435X
1.1 SPI Mode Timing Waveforms and Requirements
RESET
tRST
tRSTD
SCK
Wx
FIGURE 1-1: TABLE 1-1:
Reset Waveforms. RESET TIMING
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended)
Timing Characteristics
All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym tRST tRSTD Min 50 -- Typ -- -- Max -- 20 Units ns ns Conditions
Parameters RESET pulse width RESET rising edge normal mode (Wiper driving and SPI interface operational)
DS22242A-page 12
2010 Microchip Technology Inc.
MCP433X/435X
VIH CS 70 SCK 83 71 80 SDO MSb 75, 76 SDI 73 MSb IN 74 BIT6 - - - -1 LSb IN 79 BIT6 - - - - - -1 78 LSb 77 72 VIHH VIL 84 VIH
FIGURE 1-2: TABLE 1-2:
#
SPI Timing Waveform (Mode = 11). SPI REQUIREMENTS (MODE = 11)
Characteristic Symbol FSCK TcsA2scH TscH TscL TDIV2scH TscH2DIL TcsH2DOZ TscL2DOV TscH2csI TcsA2csI Min -- -- 60 45 500 45 500 10 20 20 -- -- 100 1 50 Max Units 10 1 -- -- -- -- -- -- -- -- 50 70 170 -- -- Conditions MHz VDD = 2.7V to 5.5V MHz VDD = 1.8V to 2.7V ns ns ns ns ns ns ns ns ns ns ns ns ms ns Note 1 VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V
SCK Input Frequency 70 71 72 73 74 77 80 83 84 CS Active (VIL or VIHH) to SCK input SCK input high time SCK input low time Setup time of SDI input to SCK edge Hold time of SDI input from SCK edge CS Inactive (VIH) to SDO output high-impedance SDO data output valid after SCK edge CS Inactive (VIH) after SCK edge Hold time of CS Inactive (VIH) to CS Active (VIL or VIHH) This specification by design.
Note 1:
2010 Microchip Technology Inc.
DS22242A-page 13
MCP433X/435X
VIH CS 70 83 71 SDO MSb 75, 76 MSb IN 74 BIT6 - - - -1 LSb IN 72 BIT6 - - - - - -1 80 LSb 77 VIHH 82 VIL VIH 84
SCK
73 SDI
FIGURE 1-3: TABLE 1-3:
#
SPI Timing Waveform (Mode = 00). SPI REQUIREMENTS (MODE = 00)
Characteristic Symbol FSCK TcsA2scH TscH TscL TDIV2scH TscH2DIL TcsH2DOZ TscL2DOV TssL2doV TscH2csI TcsA2csI Min -- -- 60 45 500 45 500 10 20 20 -- -- -- 100 1 50 Max Units 10 1 -- -- -- -- -- -- -- -- 50 70 170 85 -- -- Conditions MHz VDD = 2.7V to 5.5V MHz VDD = 1.8V to 2.7V ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V Note 1 VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V
SCK Input Frequency 70 71 72 73 74 77 80 82 83 84 CS Active (VIL or VIHH) to SCK input SCK input high time SCK input low time Setup time of SDI input to SCK edge Hold time of SDI input from SCK edge CS Inactive (VIH) to SDO output high-impedance SDO data output valid after SCK edge SDO data output valid after CS Active (VIL or VIHH) CS Inactive (VIH) after SCK edge Hold time of CS Inactive (VIH) to CS Active (VIL or VIHH) This specification by design.
Note 1:
DS22242A-page 14
2010 Microchip Technology Inc.
MCP433X/435X
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 14L-TSSOP Thermal Resistance, 20L-QFN Thermal Resistance, 20L-TSSOP JA JA JA -- -- -- 100 43 90 -- -- -- C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +125 +125 +150 C C C Sym Min Typ Max Units Conditions
2010 Microchip Technology Inc.
DS22242A-page 15
MCP433X/435X
NOTES:
DS22242A-page 16
2010 Microchip Technology Inc.
MCP433X/435X
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 0.00 250
2.7V -40C 2.7V 25C 2.7V 85C 2.7V 125C 5.5V -40C 5.5V 25C 5.5V 85C 5.5V 125C
200 RCS (kOhms) 150 100 50
RCS ICS
0 2.00 4.00 6.00 8.00 fSCK (MHz) 10.00 12.00 2 3 4 5 6 7 VCS (V) 8 9 10
1000 800 600 400 200 0 -200 -400 -600 -800 -1000
Operating Current (IDD) (A)
FIGURE 2-1: Device Current (IDD) vs. SPI Frequency (fSCK) and Ambient Temperature (VDD = 2.7V and 5.5V).
3.0 Standby Current (Istby) (A)
FIGURE 2-3: CS Pull-up/Pull-down Resistance (RCS) and Current (ICS) vs. CS Input Voltage (VCS) (VDD = 5.5V).
12 CS VPP Threshold (V) 10
5.5V Entry
2.5 2.0 1.5 1.0 0.5 0.0 -40 25 85 125 Ambient Temperature (C)
2.7V 5.5V
8 6 4
2.7V Exit 5.5V Exit
2.7V Entry
2 0 -40 -20 0 20 40 60 80 100 Ambient Temperature (C) 120
FIGURE 2-2: Device Current (ISHDN) and VDD. (CS = VDD) vs. Ambient Temperature.
FIGURE 2-4: CS High Input Entry/Exit Threshold vs. Ambient Temperature and VDD.
2010 Microchip Technology Inc.
DS22242A-page 17
ICS (A)
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
120 Wiper Resistance (RW) (ohms) 100 80 0 60 -0.1 40
125C 85C -40C 25C
Wiper Resistance (RW) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) 0.1
120 100 80 60 40
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
1.25 0.75 0.25 -0.25 Error (LSb) Error (LSb) Error (LSb)
DNL
INL
INL
RW
-0.2
125C
85C 25C
-40C
DNL RW
-0.75
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32
-1.25 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-5: 5 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (RW) (ohms) 260 220 180 0 140 100 60
-40C 25C RW 125C 85C
FIGURE 2-8: 5 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V, IW = 900 A).
300 Wiper Resistance (RW) (ohms) 260 220 180 140
RW
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) 0.1
6 4 2 0
INL DNL
INL
-0.1 -0.2
100 60
125C 85C -40C 25C
DNL
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32
-2 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-6: 5 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
0.5 0.4 0.3 0.2 1500 1000 500
RW DNL
FIGURE 2-9: 5 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V, IW = 480 A).
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
118 98 78 58 38
Wiper Resistance (RW) (ohms)
Wiper Resistance (RW) (ohms)
2500 2000
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
2500 2000 1500 1000 500
INL
INL
0.1 0
-0.1 -0.2 -0.3 256
Error (LSb)
RW
DNL
18 -2 256
0 0 64 128 192 Wiper Setting (decimal)
0 0 64 128 192 Wiper Setting (decimal)
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-7: 5 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V).
FIGURE 2-10: 5 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V, IW = 260 A).
DS22242A-page 18
2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
5300
6000 5000
2.7V
Nominal Resistance (RAB) (Ohms)
5250 5200 5150
5.5V
Resistance ()
4000 3000 2000 1000 -40C +25C +85C +125C 0 32 64 96 128 160 Wiper Code 192 224 256
5100 5050 -40
1.8V
0 40 80 Ambient Temperature (C)
120
0
FIGURE 2-11: 5 k - Nominal Resistance (RAB) () vs. Ambient Temperature and VDD.
FIGURE 2-12: 5 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 5.5V, IW = 190 A).
6000 5000 Resistance () 4000 3000 2000 1000 0 0 32 64 96 128 160 Wiper Code 192 224 256 -40C +25C +85C +125C
FIGURE 2-13: 5 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 3.0V, IW = 190 A).
7000 6000 Resistance () 5000 4000 3000 2000 1000 0 0 32 64 96 128 160 Wiper Code 192 224 256 -40C +25C +85C +125C
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-14: 5 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 1.8V, IW = 190 A).
2010 Microchip Technology Inc.
DS22242A-page 19
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
2.50% 1.50% 0.50% -0.50% -1.50% -2.50% 0 32 64 96 128 160 192 224 256 Wiper Code
-40C +25C +85C +125C
54 52 50 PPM / C 48 46 44 42 40 0 32 64 96 128 160 Wiper Code 192 224 256
CH0 CH2 CH1 CH3
Error %
FIGURE 2-15: 5 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 5.5V, IW = 190 A).
2.50% 1.50% 0.50% -0.50% -1.50% -2.50% 0 32 64 96 128 160 192 224 256
FIGURE 2-18: 5 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, -40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 5.5V, IW = 190 A).
100 95 90 PPM / C 85 80 75 70 65 60 0 32 64 96 128 160 Wiper Code 192 224 256
-40C +25C +85C +125C
CH0 CH2
CH1 CH3
Error %
Wiper Code
FIGURE 2-16: 5 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 3.0V, IW = 190 A).
2.00% 1.00% 0.00%
FIGURE 2-19: 5 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, -40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 3.0V, IW = 190 A).
500 0 PPM / C -500 -1000 -1500 -2000
-1.00%
Error %
-2.00% -3.00% -4.00% -5.00% -6.00% -7.00% 0 32 64 96 128 160 192
-40C +25C +85C +125C
224 256
CH0 CH2
0 32 64
CH1 CH3
96 128 160 Wiper Code 192 224 256
Wiper Code
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-17: 5 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 1.8V, IW = 190 A).
FIGURE 2-20: 5 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, -40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 1.8V, IW = 190 A).
DS22242A-page 20
2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
FIGURE 2-21: 5 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-24: 5 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-22: 5 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-25: 5 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-23: 5 k - Power-Up Wiper Response Time (20 ms/Div).
2010 Microchip Technology Inc.
DS22242A-page 21
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
120 Wiper Resistance (RW) (ohms) 100 80 0 60 -0.1 40 20 0 64 128 192 Wiper Setting (decimal)
25C -40C 125C 85C
Wiper Resistance (RW) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) 0.1
120 100 80
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
1
0.5 Error (LSb) Error (LSb) Error (LSb)
INL
DNL
INL
0 60 40
125C -40C
RW
-0.2 -0.3 256
85C 25C
RW
DNL
-0.5
20 0 32
-1 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-26: 10 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (RW) (ohms) 260 220 180 0 140 100 60 20 0 32
25C 125C 85C -40C
FIGURE 2-29: 10 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V, IW = 450 A).
300 Wiper Resistance (RW) (ohms) 260 220 180 1 140 100 60
125C 85C 25C -40C
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) 0.1
4 3 2
INL
DNL
INL
RW
-0.1 -0.2
0
DNL RW
-1 -2 256
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 64 128 192 Wiper Setting (decimal)
FIGURE 2-27: 10 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
0.6
FIGURE 2-30: 10 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V, IW = 240 A).
98 88 78 68 58 48 38 28 18 8 -2 256
4000 Wiper Resistance (RW)(ohms) 3500 3000 2500 2000 1500 1000 500 0 0
Wiper Resistance (RW) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.5 0.4 Error (LSb) 0.3 0.2 0.1 0
4000 3500 3000 2500 2000 1500 1000 500 0 0
-40C Rw 125C Rw 85C INL 25C DNL
25C Rw -40C INL 125C INL 85C DNL
85C Rw 25C INL -40C DNL 125C DNL
INL
INL
DNL
-0.1
RW
-0.2 -0.3 256
RW
DNL
64 128 192 Wiper Setting (decimal)
64 128 192 Wiper Setting (decimal)
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-28: 10 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V).
FIGURE 2-31: 10 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V, IW = 125 A).
DS22242A-page 22
2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
10300
12000 10000 Resistance () 8000 6000 4000 2000 0 0 32 64 96 128 160 Wiper Code 192 224 256
-40C +25C +85C +125C
Nominal Resistance (RAB) (Ohms)
10250 10200 10150 10100 10050 10000 9950 9900 9850 -40 0 40 80 Ambient Temperature (C) 120
1.8V 5.5V 2.7V
FIGURE 2-32: 10 k - Nominal Resistance (RAB) () vs. Ambient Temperature and VDD.
FIGURE 2-33: 10 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 5.5V, IW = 150 A).
12000 10000 Resistance () 8000 6000 4000 2000 0 0 32 64 96 128 160 Wiper Code 192 224 256
-40C +25C +85C +125C
FIGURE 2-34: 10 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 3.0V, IW = 150 A).
12000 10000 Resistance () 8000 6000 4000 2000 0 0 32 64 96 128 160 Wiper Code 192 224 256
-40C +25C +85C +125C
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-35: 10 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 1.8V, IW = 150 A).
2010 Microchip Technology Inc.
DS22242A-page 23
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
1.50% 1.00% 0.50% Error % 0.00% -0.50% -1.00% -1.50% 0 32 64 96 128 160 192 224 256 Wiper Code
-40C +85C
+25C +125C
50 45 40 PPM / C 35 30 25 20 15 10 0 32 64 96 128 160 Wiper Code 192 224 256
CH0 CH2 CH1 CH3
FIGURE 2-36: 10 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 5.5V, IW = 150 A).
1.50% 1.00% 0.50% Error % 0.00% -0.50% -1.00% -1.50% 0 32 64 96 128 160 192 224 256 Wiper Code
FIGURE 2-39: 10 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, -40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 5.5V, IW = 150 A).
60 55 50 PPM / C 45 40 35 30 25 20 0 32 64 96 128 160 Wiper Code 192 224 256
CH0 CH2 CH1 CH3
-40C +85C
+25C +125C
FIGURE 2-37: 10 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 3.0V, IW = 150 A).
1.50% 1.00% 0.50% Error % 0.00% -0.50% -1.00% -1.50%
0 32 64 96 128 160 192 224 256
FIGURE 2-40: 10 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, -40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 3.0V, IW = 150 A).
200 0 -200 PPM / C -400 -600 -800 -1000 -1200 -1400 0 32 64
CH0 CH2 CH1 CH3
-40C +85C
+25C +125C
Wiper Code
96 128 160 192 224 256 Wiper Code
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-38: 10 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 1.8V, IW = 150 A).
DS22242A-page 24
FIGURE 2-41: 10 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, -40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 1.8V, IW = 150 A).
2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
FIGURE 2-42: 10 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-44: 10 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-43: 10 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-45: 10 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div).
2010 Microchip Technology Inc.
DS22242A-page 25
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
120 Wiper Resistance (RW) (ohms) 100 80 0 60 -0.1 40
125C 25C 85C -40C
Wiper Resistance (RW) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) 0.1
120 100 80
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) Error (LSb) Error (LSb) 0.1 0
DNL
INL
INL DNL
60 -0.1 40
125C 85C 25C -40C
RW
-0.2
RW
-0.2
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-46: 50 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (RW) (ohms) 260 220 180 0 140 100 60
125C 85C 25C -40C
FIGURE 2-49: 50 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V, IW = 90 A).
300 Wiper Resistance (RW) (ohms) 260 220 180 140 100 60
125C -40C 85C 25C
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) 0.1
1 0.75 0.5 0.25 0
INL DNL
DNL
INL
RW
-0.1 -0.2
RW
-0.25 -0.5 -0.75
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32 64
-1 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-47: 50 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
FIGURE 2-50: 50 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V, IW = 48 A).
15000 14000 13000 12000 11000 10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 78.5 73.5 68.5 63.5 58.5 53.5 48.5 43.5 38.5 33.5 28.5 23.5 18.5 13.5 8.5 3.5 -1.5
15000 14000 13000 12000 11000 10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 0
Wiper Resistance (RW) (ohms)
Wiper Resistance (Rw) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
INL RW
Error (LSb)
DNL
64 128 192 Wiper Setting (decimal)
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 256
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
RW INL
DNL
0
64
128
192
256
Wiper Setting (decimal)
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-48: 50 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V).
FIGURE 2-51: 50 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V, IW = 25 A).
DS22242A-page 26
2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
52500
60000 50000 Resistance ()
1.8V
Nominal Resistance (RAB) (Ohms)
52000 51500 51000 50500 50000 49500 49000 -40 0 40 80 Ambient Temperature (C) 120
2.7V 5.5V
40000 30000 20000 10000 0 0 32 64 96 128 160 Wiper Code 192 224 256
-40C +25C +85C +125C
FIGURE 2-52: 50 k - Nominal Resistance (RAB) () vs. Ambient Temperature and VDD.
FIGURE 2-53: 50 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 5.5V, IW = 90 A).
60000 50000 Resistance () 40000 30000 20000 10000 0 0 32 64 96 128 160 Wiper Code 192
-40C +25C +85C +125C
224 256
FIGURE 2-54: 50 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 3.0V, IW = 48 A).
60000 50000 Resistance () 40000 30000 20000 10000 0 0 32 64 96 128 160 Wiper Code 192
-40C +25C +85C +125C
224 256
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-55: 50 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 1.8V, IW = 30 A).
2010 Microchip Technology Inc.
DS22242A-page 27
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
7.00% 6.00% 5.00%
-40C +85C
+25C +125C
3.00% 2.00% 1.00% 0.00% -1.00% 0 32 64 96 128 160 192 224 256 Wiper Code
PPM / C
Error %
4.00%
7 6 5 4 3 2 1 0 -1 -2 -3 0
CH0 CH2
CH1 CH3
32
64
96 128 160 Wiper Code
192
224
256
FIGURE 2-56: 50 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 5.5V, IW = 90 A).
4.00% 3.00% 2.00% Error % 1.00% 0.00% -1.00% -2.00% 0 32 64 96 128 160 192 224 256 Wiper Code
FIGURE 2-59: 50 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, -40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 5.5V, IW = 90 A).
12
-40C +85C
+25C +125C
10 8 PPM / C 6 4 2 0 -2 0 32 64 96 128 160 Wiper Code 192 224 256
CH0 CH2 CH1 CH3
FIGURE 2-57: 50 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 3.0V, IW = 48 A).
3.50% 2.50% 1.50% 0.50% -0.50% -1.50% 0 32 64 96 128 160 192 224 256 Wiper Code
FIGURE 2-60: 50 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, -40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 3.0V, IW = 48 A).
200 0 -200 PPM / C -400 -600 -800 -1000 -1200 -1400 0 32 64 96 128 160 192 224 256 Wiper Code
CH0 CH2 CH1 CH3
-40C +85C
+25C +125C
Error %
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-58: 50 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 1.8V, IW = 30 A).
DS22242A-page 28
FIGURE 2-61: 50 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, -40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 1.8V, IW = 30 A).
2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
FIGURE 2-62: 50 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-64: 50 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-63: 50 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-65: 50 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div).
2010 Microchip Technology Inc.
DS22242A-page 29
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
120 Wiper Resistance (RW) (ohms) 100 80 60 40 20 0 32 -0.1
25C -40C 125C 85C
Wiper Resistance (RW) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.2
120 100 80 60
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) Error (LSb) Error (LSb) 0.1 0 -0.1
Error (LSb)
INL DNL
0.1
INL DNL
0
RW
40
125C 85C 25C
-40C
RW
-0.2
-0.2 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-66: 100 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (RW) (ohms) 260 220 180 140 100 60 20 0
125C 85C 25C -40C
FIGURE 2-69: 100 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V, IW = 45 A).
300 Wiper Resistance (Rw) (ohms) 260 220
DNL
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.2 0.15 0.1 0.05 0 Error (LSb)
0.6 0.4 0.2 0
INL
INL DNL
180 140 100 60
125C 85C 25C -40C
-0.05
RW
RW
-0.2 -0.4
-0.1 -0.15
32
-0.2 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32
-0.6 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-67: 100 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
0.35 0.25
FIGURE 2-70: 100 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V, IW = 24 A).
59 54 49 RW 44 39 INL 34 29 24 19 14 9 4 -1 256
Wiper Resistance (RW) (ohms)
25000 20000 15000 10000 5000
0.05
Error (LSb)
DNL
0.15
Wiper Resistance (RW) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
25000 20000 15000 10000 5000
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
-0.05 -0.15
RW INL
-0.25 -0.35
DNL
0 0 64 128 192 Wiper Setting (decimal)
0 0 64 128 192 Wiper Setting (decimal)
256
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-68: 100 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V).
FIGURE 2-71: 100 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V, IW = 10 A).
DS22242A-page 30
2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
103500 103000 102500 102000 101500 101000 100500 100000 99500 99000 98500 -40
120000 100000 Resistance () 80000 60000 40000 20000
Nominal Resistance (RAB) (Ohms)
1.8V
2.7V 5.5V
0 40 80 Ambient Temperature (C)
120
0 0 32 64 96 128 160 Wiper Code 192
-40C +25C +85C +125C
224 256
FIGURE 2-72: 100 k - Nominal Resistance (RAB) () vs. Ambient Temperature and VDD .
FIGURE 2-73: 100 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 5.5V, IW = 45 A).
120000 100000 Resistance () 80000 60000 40000 20000 0 0 32 64 96 128 160 Wiper Code 192 224 256
-40C +25C +85C +125C
FIGURE 2-74: 100 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 3.0V, IW = 24 A).
120000 100000 Resistance () 80000 60000 40000 20000 0 0 32 64 96 128 160 Wiper Code 192 224 256
-40C +25C +85C +125C
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-75: 100 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 1.8V, IW = 15 A).
2010 Microchip Technology Inc.
DS22242A-page 31
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
14.00% 13.00% 12.00% 11.00% 10.00% 9.00% 8.00% 7.00% 6.00% 5.00% 4.00% 3.00% 2.00% 1.00% 0.00% -1.00% 0 32 64 96 128 Wiper Code
-40C +85C
+25C +125C
16 14 12 PPM / C 10 8 6 4 2 0
CH0 CH2 CH1 CH3
Error %
160
192
224
256
0
32
64
96 128 160 Wiper Code
192
224
256
FIGURE 2-76: 100 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 5.5V, IW = 45 A).
7.00% 6.00% 5.00%
FIGURE 2-79: 100 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, -40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 5.5V, IW = 45 A).
18 16 14 PPM / C 12 10 8 6 4 2 0
CH0 CH2 CH1 CH3
-40C +85C
+25C +125C
Error %
4.00% 3.00% 2.00% 1.00% 0.00% -1.00% 0 32 64 96 128 160 192 224 256 Wiper Code
0
32
64
96 128 160 Wiper Code
192
224
256
FIGURE 2-77: 100 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 3.0V, IW = 24 A).
6.00% 5.00% 4.00%
FIGURE 2-80: 100 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, -40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 3.0V, IW = 24 A).
200
-40C +85C
+25C +125C
0 -200 PPM / C -400 -600 -800 -1000 -1200
CH0 CH2 CH1 CH3
Error %
3.00% 2.00% 1.00% 0.00% -1.00% 0 32 64 96 128 160 192 224 256 Wiper Code
0
32
64
96 128 160 192 224 256 Wiper Code
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-78: 100 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 1.8V, IW = 15 A).
DS22242A-page 32
FIGURE 2-81: 100 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, -40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 1.8V, IW = 15 A).
2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
FIGURE 2-82: 100 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-84: 100 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-83: 100 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-85: 100 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div).
2010 Microchip Technology Inc.
DS22242A-page 33
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
2.4 2.2
5.5V
0 -5 -10 IOH (mA) -15 -20 -25 -30 -35 -40 -45 -40 0 40 Temperature (C) 80 120 -40 0 40 Temperature (C) 80 120
5.5V 2.7V
2 VIH (V) 1.8 1.6 1.4 1.2 1
2.7V
FIGURE 2-86: VIH (SDI, SCK, CS, and RESET) vs. VDD and Temperature.
1.4 1.3 1.2 VIL (V) 1.1 1 0.9 0.8 0.7 0.6 -40 0 40 Temperature (C) 80 120
2.7V 5.5V
FIGURE 2-88: Temperature.
50 45 40 35 30 25 20 15 10 5 0 -40 0
IOH (SDO) vs. VDD and
5.5V
IOL (mA)
2.7V
40 Temperature (C)
80
120
FIGURE 2-87: VIL (SDI, SCK, CS, and RESET) vs. VDD and Temperature.
FIGURE 2-89: Temperature.
IOL (SDO) vs. VDD and
DS22242A-page 34
2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
2.1
Test Circuits
2 1.6 VDD (V) 1.2 0.8 0.4 0 -40 0 40 Temperature (C) 80 120
+5V VIN Offset GND A B W + VOUT
2.5V DC
FIGURE 2-90: and Temperature.
14.2 14.1 14.0 fsck (MHz) 13.9 13.8 13.7 13.6 13.5 13.4 -40 0
POR/BOR Trip point vs. VDD
FIGURE 2-92: Measurement.
floating VA A W
-3 db Gain vs. Frequency
5.5V
VW IW
2.7V
B
RBW = VW / IW RW = (VW - VA) / IW
VB
40 Temperature (C)
80
120
FIGURE 2-93:
RBW and RW Measurement.
FIGURE 2-91: SCK Input Frequency vs. Voltage and Temperature.
2010 Microchip Technology Inc.
DS22242A-page 35
MCP433X/435X
NOTES:
DS22242A-page 36
2010 Microchip Technology Inc.
MCP433X/435X
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follows.
TABLE 3-1:
TSSOP 14L -- 1 2 3 4 5 6 7 8 -- -- 9 10 -- -- 11 12 13 14 -- -- Legend: 20L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 --
PINOUT DESCRIPTION FOR THE MCP433X/435X
Pin QFN 20L 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 21 Symbol P3A P3W P3B CS SCK SDI VSS P1B P1W P1A P0A P0W P0B NC RESET SDO VDD P2B P2W P2A EP I/O A A A I I I -- A A A A A A I I O -- A A A -- Buffer Type Analog Analog Analog HV w/ST HV w/ST HV w/ST P Analog Analog Analog Analog Analog Analog I HV w/ST O P Analog Analog Analog -- Weak Pull-up/ down (Note 1) No No No "smart" "smart" "smart" -- No No No No No No -- Yes No -- No No No -- Standard Function
Potentiometer 3 Terminal A Potentiometer 3 Wiper Terminal Potentiometer 3 Terminal B SPI Chip Select Input SPI Clock Input SPI Serial Data Input Ground Potentiometer 1 Terminal B Potentiometer 1 Wiper Terminal Potentiometer 1 Terminal A Potentiometer 0 Terminal A Potentiometer 0 Wiper Terminal Potentiometer 0 Terminal B No Connect Hardware Reset Pin SPI Serial Data Output Positive Power Supply Input Potentiometer 2 Terminal B Potentiometer 2 Wiper Terminal Potentiometer 2 Terminal A Exposed Pad. (Note 2)
HV w/ST = High Voltage tolerant input (with Schmitt trigger input) A = Analog pins (Potentiometer terminals) I = digital input (high Z) O = digital output I/O = Input / Output P = Power The pin's "smart" pull-up shuts off while the pin is forced low. This is done to reduce the standby and shutdown current. The QFN package has a contact on the bottom of the package. This contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device's VSS pin.
Note 1: 2:
2010 Microchip Technology Inc.
DS22242A-page 37
MCP433X/435X
3.1 Chip Select (CS) 3.7 Potentiometer Terminal A
The CS pin is the serial interface's chip select input. Forcing the CS pin to VIL enables the serial commands. Forcing the CS pin to VIHH enables the high-voltage serial commands. The terminal A pin is available on the MCP43X1 devices, and is connected to the internal potentiometer's terminal A. The potentiometer's terminal A is the fixed connection to the full scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x100 for 8-bit devices or 0x80 for 7-bit devices. The terminal A pin does not have a polarity relative to the terminal W or B pins. The terminal A pin can support both positive and negative current. The voltage on terminal A must be between VSS and VDD. The terminal A pin is not available on the MCP43X2 devices, and the internally terminal A signal is floating. MCP43X1 devices have four terminal A pins, one for each resistor network.
3.2
Serial Clock (SCK)
The SCK pin is the serial interface's Serial Clock pin. This pin is connected to the host controllers SCK pin. The MCP43XX is an SPI slave device, so it's SCK pin is an input only pin.
3.3
Serial Data In (SDI)
The SDI pin is the serial interfaces Serial Data In pin. This pin is connected to the host controllers SDO pin.
3.4
Ground (VSS)
The VSS pin is the device ground reference.
3.8
Not Connected (NC)
The NC pin is not used.
3.5
Potentiometer Terminal B
The terminal B pin is connected to the internal potentiometer's terminal B. The potentiometer's terminal B is the fixed connection to the zero scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices. The terminal B pin does not have a polarity relative to the terminal W or A pins. The terminal B pin can support both positive and negative current. The voltage on terminal B must be between VSS and VDD. MCP43XX devices have four terminal B pins, one for each resistor network.
3.9
Reset (RESET)
The RESET pin is used to force the device into the POR/BOR state.
3.10
Serial Data Out (SDO)
The SDO pin is the serial interfaces Serial Data Out pin. This pin is connected to the host controllers SDI pin. This pin allows the host controller to read the digital potentiometers registers, or monitor the state of the command error bit.
3.11
Positive Power Supply Input (VDD)
3.6
Potentiometer Wiper (W) Terminal
The VDD pin is the device's positive power supply input. The input power supply is relative to VSS. While the devices VDD is less than Vmin (2.7V), the electrical performance of the device may not meet the data sheet specifications.
The terminal W pin is connected to the internal potentiometer's terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The terminal W pin does not have a polarity relative to terminals A or B pins. The terminal W pin can support both positive and negative current. The voltage on terminal W must be between VSS and VDD. MCP43XX devices have four terminal W pins, one for each resistor network.
3.12
Exposed Pad (EP)
This pad is conductively connected to the device's substrate. This pad should be tied to the same potential as the VSS pin (or left unconnected). This pad could be used to assist as a heat sink for the device when connected to a PCB heat sink.
DS22242A-page 38
2010 Microchip Technology Inc.
MCP433X/435X
4.0 FUNCTIONAL OVERVIEW
4.1.2 BROWN-OUT RESET
This data sheet covers a family of four volatile Digital Potentiometer and Rheostat devices that will be referred to as MCP43XX. The MCP43X1 devices are the Potentiometer configuration, while the MCP43X2 devices are the Rheostat configuration. As the Device Block Diagram shows, there are four main functional blocks. These are: * * * * POR/BOR and Reset Operation Memory Map Resistor Network Serial Interface (SPI) When the device powers down, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage decreases below the VPOR/VBOR voltage the following happens: * Serial Interface is disabled If the VDD voltage decreases below the VRAM voltage, the following happens: * Volatile wiper registers may become corrupted * TCON registers may become corrupted As the voltage recovers above the VPOR/VBOR voltage, the operation is the same as Power-on Reset (see Section 4.1.1 "Power-on Reset"). Serial commands not completed due to a brown-out condition may cause the memory location to become corrupted. 4.1.3 RESET PIN
The POR/BOR operation and the Memory Map are discussed in this section and the Resistor Network and SPI operation are described in their own sections. The Device Commands are discussed in Section 7.0.
4.1
POR/BOR and Reset Operation
The Power-on Reset is the case where the device is having power applied to it from VSS. The Brown-out Reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. The devices RAM retention voltage (VRAM) is lower than the POR/BOR voltage trip point (VPOR/VBOR). The maximum VPOR/VBOR voltage is less than 1.8V. When VPOR/VBOR < VDD < 2.7V, the analog electrical performance may not meet the data sheet specifications. In this region, the device is capable of incrementing, decrementing, reading and writing to its volatile memory, if the proper serial command is executed. When VDD < VPOR/VBOR or the RESET pin is Low, the pin weak pull-ups are enabled.
The RESET pin can be used to force the device into the POR/BOR state of the device. When the RESET pin is forced Low, the device is forced into the Reset state. This means that the TCON registers are forced to their default values and the volatile wiper registers are loaded with the default value. Also the SPI interface is disabled. This feature allows a hardware method for all registers to be updated to the default value at the same time. 4.1.4 INTERACTION OF RESET PIN AND BOR/ POR CIRCUITRY
Figure 4-1 shows how the RESET pin signal and the POR/BOR signal interact to control the hardware Reset state of the device. RESET (from pin) POR/BOR signal
4.1.1
POWER-ON RESET
Device Reset
When the device powers up, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage crosses the VPOR/VBOR voltage, the following happens: * Volatile wiper register is loaded with the default value * The TCON registers are loaded with their default value * The device is capable of digital operation
FIGURE 4-1: POR/BOR Signal and RESET Pin Interaction.
2010 Microchip Technology Inc.
DS22242A-page 39
MCP433X/435X
4.2 Memory Map
The device memory supports 16 locations that are 9-bits wide (16x9 bits). This memory space contains only volatile locations (see Table 4-2). The volatile memory starts functioning at the RAM retention voltage (VRAM). The POR/BOR Wiper code is shown in Table 4-1.
TABLE 4-1:
STANDARD SETTINGS
Wiper Default Code POR Wiper Setting 8-bit 7-bit Mid scale Mid scale Mid scale Mid scale 80h 80h 80h 80h 40h 40h 40h 40h
4.2.1
* * * * * *
VOLATILE MEMORY (RAM)
There are six volatile memory locations. These are: Volatile Wiper 0 Volatile Wiper 1 Volatile Wiper 2 Volatile Wiper 3 Terminal Control (TCON0) Register 0 Terminal Control (TCON)1 Register 1
Resistance Typical Code RAB Value -502 -103 -503 -104 5.0 k 10.0 k 50.0 k 100.0 k
TABLE 4-2:
Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah
MEMORY MAP AND THE SUPPORTED COMMANDS
Function Memory Type RAM RAM -- -- RAM -- RAM RAM -- -- RAM -- Allowed Commands Read, Write, Increment, Decrement Read, Write, Increment, Decrement None None Read, Write None Read, Write, Increment, Decrement Read, Write, Increment, Decrement None None Read, Write None Disallowed Commands (1) -- -- All All Increment, Decrement All -- -- All All Increment, Decrement All 7-bit 8-bit 7-bit 8-bit -- -- 1FFh -- Factory Initialization 7-bit 8-bit 7-bit 8-bit -- -- 1FFh -- 040h 080h 040h 080h 040h 080h 040h 080h
Volatile Wiper 0 Volatile Wiper 1 Reserved Reserved Volatile TCON0 Register Reserved Volatile Wiper 2 Volatile Wiper 3 Reserved Reserved Volatile TCON1 Register
0Bh-0Fh Reserved Note 1:
This command on this address will generate an error condition. To exit the error condition, the user must take the CS pin to the VIH level and then back to the active state (VIL or VIHH).
DS22242A-page 40
2010 Microchip Technology Inc.
MCP433X/435X
4.2.1.1 Terminal Control (TCON) Registers
There are two Terminal Control (TCON) Registers. These are called TCON0 and TCON1. Each register contains 8 control bits. Four bits for each Wiper. Register 4-1 describes each bit of the TCON0 register, while Register 4-2 describes each bit of the TCON1 register. The state of each resistor network terminal connection is individually controlled. That is, each terminal connection (A, B and W) can be individually connected/ disconnected from the resistor network. This allows the system to minimize the currents through the digital potentiometer. The value that is written to the specified TCON register will appear on the appropriate resistor network terminals when the serial command has completed. On a POR/BOR these registers are loaded with 1FFh (9-bits), for all terminals connected. The host controller needs to detect the POR/BOR event and then update the volatile TCON register values. R/W-1 R1B R/W-1 R0HW R/W-1 R0A R/W-1 R0W R/W-1 R0B bit 0
REGISTER 4-1:
R-1 D8 bit 8 Legend: R = Readable bit -n = Value at POR bit 8 bit 7
TCON0 BITS (1)
R/W-1 R1A R/W-1 R1W
R/W-1 R1HW
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
D8: Reserved. Forced to "1" R1HW: Resistor 1 Hardware Configuration Control bit This bit forces Resistor 1 into the "shutdown" configuration of the Hardware pin 1 = Resistor 1 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 1 is forced to the hardware pin "shutdown" configuration R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network 1 = P1A pin is connected to the Resistor 1 Network 0 = P1A pin is disconnected from the Resistor 1 Network R1W: Resistor 1 Wiper (P1W pin) Connect Control bit This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network 1 = P1W pin is connected to the Resistor 1 Network 0 = P1W pin is disconnected from the Resistor 1 Network R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network 1 = P1B pin is connected to the Resistor 1 Network 0 = P1B pin is disconnected from the Resistor 1 Network R0HW: Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the "shutdown" configuration of the Hardware pin 1 = Resistor 0 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 0 is forced to the hardware pin "shutdown" configuration R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network 1 = P0A pin is connected to the Resistor 0 Network 0 = P0A pin is disconnected from the Resistor 0 Network R0W: Resistor 0 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network 1 = P0W pin is connected to the Resistor 0 Network 0 = P0W pin is disconnected from the Resistor 0 Network R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network 1 = P0B pin is connected to the Resistor 0 Network 0 = P0B pin is disconnected from the Resistor 0 Network These bits do not affect the wiper register values.
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bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2010 Microchip Technology Inc.
MCP433X/435X
REGISTER 4-2:
R-1 D8 bit 8 Legend: R = Readable bit -n = Value at POR bit 8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TCON1 BITS (1)
R/W-1 R3A R/W-1 R3W R/W-1 R3B R/W-1 R2HW R/W-1 R2A R/W-1 R2W R/W-1 R2B bit 0
R/W-1 R3HW
D8: Reserved. Forced to "1" R3HW: Resistor 3 Hardware Configuration Control bit This bit forces Resistor 3 into the "shutdown" configuration of the Hardware pin 1 = Resistor 3 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 3 is forced to the hardware pin "shutdown" configuration R3A: Resistor 3 Terminal A (P3A pin) Connect Control bit This bit connects/disconnects the Resistor 3 Terminal A to the Resistor 3 Network 1 = P3A pin is connected to the Resistor 3 Network 0 = P3A pin is disconnected from the Resistor 3 Network R3W: Resistor 3 Wiper (P3W pin) Connect Control bit This bit connects/disconnects the Resistor 3 Wiper to the Resistor 3 Network 1 = P3W pin is connected to the Resistor 3 Network 0 = P3W pin is disconnected from the Resistor 3 Network R3B: Resistor 3 Terminal B (P3B pin) Connect Control bit This bit connects/disconnects the Resistor 3 Terminal B to the Resistor 3 Network 1 = P3B pin is connected to the Resistor 3 Network 0 = P3B pin is disconnected from the Resistor 3 Network R2HW: Resistor 2 Hardware Configuration Control bit This bit forces Resistor 2 into the "shutdown" configuration of the Hardware pin 1 = Resistor 2 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 2 is forced to the hardware pin "shutdown" configuration R2A: Resistor 2 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 2 Terminal A to the Resistor 2 Network 1 = P2A pin is connected to the Resistor 2 Network 0 = P2A pin is disconnected from the Resistor 2 Network R2W: Resistor 2 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 2 Wiper to the Resistor 2 Network 1 = P2W pin is connected to the Resistor 2 Network 0 = P2W pin is disconnected from the Resistor 2 Network R2B: Resistor 2 Terminal B (P2B pin) Connect Control bit This bit connects/disconnects the Resistor 2 Terminal B to the Resistor 2 Network 1 = P2B pin is connected to the Resistor 2 Network 0 = P2B pin is disconnected from the Resistor 2 Network These bits do not affect the wiper register values.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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5.0 RESISTOR NETWORK
5.1 Resistor Ladder Module
The Resistor Network has either 7-bit or 8-bit resolution. Each Resistor Network allows zero scale to full scale connections. Figure 5-1 shows a block diagram for the resistive network of a device. The Resistor Network is made up of several parts. These include: * Resistor Ladder * Wiper * Shutdown (Terminal Connections) Devices have either four resistor networks. These are referred to as Pot 0, Pot 1, Pot 2 and Pot 3. The resistor ladder is a series of equal value resistors (RS) with a connection point (tap) between the two resistors. The total number of resistors in the series (ladder) determines the RAB resistance (see Figure 5-1). The end points of the resistor ladder are connected to analog switches which are connected to the device terminal A and terminal B pins. The RAB (and RS) resistance has small variations over voltage and temperature. For an 8-bit device, there are 256 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 256 resistors thus providing 257 possible settings (including terminal A and terminal B). For a 7-bit device, there are 128 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 128 resistors thus providing 129 possible settings (including terminal A and terminal B). Equation 5-1 shows the calculation for the step resistance.
A
8-Bit N= 257 (1) (100h) 256 (1) (FFh) 255 (FEh) 7-Bit N= 128 (80h) 127 (7Fh) 126 (7Eh)
RS
RW
RS
RW RW
EQUATION 5-1:
RAB RS = ------------ 256
RS CALCULATION
8-bit Device
R RAB S
(1)
W
RW 1 (1) (01h) 0 (00h) 1 (01h) 0 (00h)
R AB R S = ------------ 128
7-bit Device
RS
RW
(1)
Analog Mux
B
Note 1: The wiper resistance is dependent on several factors including, wiper code, device VDD, Terminal voltages (on A, B and W), and temperature. Also for the same conditions, each tap selection resistance has a small variation. This RW variation has greater effects on some specifications (such as INL) for the smaller resistance devices (5.0 k) compared to larger resistance devices (100.0 k).
FIGURE 5-1:
Resistor Block Diagram.
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5.2 Wiper
TABLE 5-1:
Wiper Setting 7-bit 3FFh081h 080h 07Fh041h 040h 03Fh001h 000h 8-bit 3FFh101h 100h 0FFh081h 080h 07Fh001h 000h Each tap point (between the RS resistors) is a connection point for an analog switch. The opposite side of the analog switch is connected to a common signal which is connected to the Terminal W (Wiper) pin. A value in the volatile wiper register selects which analog switch to close, connecting the W terminal to the selected node of the resistor ladder. The wiper can connect directly to Terminal B or to Terminal A. A zero scale connection, connects the Terminal W (wiper) to Terminal B (wiper setting of 000h). A full scale connection, connects the Terminal W (wiper) to Terminal A (wiper setting of 100h or 80h). In these configurations the only resistance between the Terminal W and the other Terminal (A or B) is that of the analog switches. A wiper setting value greater than full scale (wiper setting of 100h for 8-bit device or 80h for 7-bit devices) will also be a full scale setting (Terminal W (wiper) connected to Terminal A). Table 5-1 illustrates the full wiper setting map. Equation 5-2 illustrates the calculation used to determine the resistance between the wiper and terminal B.
VOLATILE WIPER VALUE VS. WIPER POSITION MAP
Properties Reserved (Full Scale (W = A)), Increment and Decrement commands ignored Full Scale (W = A), Increment commands ignored W=N W = N (Mid Scale) W=N Zero Scale (W = B) Decrement command ignored
EQUATION 5-2:
RWB CALCULATION
8-bit Device
R AB N R WB = ------------- + R W 256 N = 0 to 256 (decimal) R AB N R WB = ------------- + R W 128 N = 0 to 128 (decimal)
7-bit Device
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MCP433X/435X
5.3 Shutdown
Shutdown is used to minimize the device's current consumption. The MCP43XX has one method to achieve this: * Terminal Control Register (TCON) This is different from the MCP42XXX devices in that the Hardware Shutdown pin (SHDN) has been replaced by a RESET pin. The Hardware Shutdown pin function is still available via software commands to the TCON register. The RxHW bit does NOT corrupt the values in the Volatile Wiper Registers nor the TCON register. When the Shutdown mode is exited (RxHW bit = 1): * The device returns to the Wiper setting specified by the Volatile Wiper value * The TCON register bits return to controlling the terminal connection state A Resistor Network W
5.3.1
TERMINAL CONTROL REGISTER (TCON)
The Terminal Control (TCON) register is a volatile register used to configure the connection of each resistor network terminal pin (A, B and W) to the Resistor Network. These registers are shown in Register 4-1 and Register 4-2. The RxHW bit forces the selected resistor network into the same state as the MCP42X1's SHDN pin. Alternate low-power configurations may be achieved with the RxA, RxW and RxB bits. When the RxHW bit is "0": * The P0A, P1A, P2A and P3A terminals are disconnected * The P0W, P1W, P2W and P3W terminals are simultaneously connect to the P0B, P1B, P2B and P3B terminals, respectively (see Figure 5-2) Note: When the RxHW bit forces the resistor network into the hardware SHDN state, the state of the TCON0 or TCON1 register's RxA, RxW and RxB bits is overridden (ignored). When the state of the RxHW bit no longer forces the resistor network into the hardware SHDN state, the TCON0 or TCON1 register's RxA, RxW and RxB bits return to controlling the terminal connection state. In other words, the RxHW bit does not corrupt the state of the RxA, RxW and RxB bits.
B
FIGURE 5-2: Resistor Network Shutdown State (RxHW = 0).
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NOTES:
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MCP433X/435X
6.0 SERIAL INTERFACE (SPI)
The MCP43XX devices support the SPI serial protocol. This SPI operates in the Slave mode (does not generate the serial clock). The SPI interface uses up to four pins. These are: * * * * CS - Chip Select SCK - Serial Clock SDI - Serial Data In SDO - Serial Data Out Typical SPI Interface Connections Host Controller MCP4XXX SDO SDI SCK I/O (1) (Master Out - Slave In (MOSI)) (Master In - Slave Out (MISO)) SDI SDO SCK CS Typical SPI Interface is shown in Figure 6-1. In the SPI interface, the Master's Output pin is connected to the Slave's Input pin and the Master's Input pin is connected to the Slave's Output pin. The MCP4XXX SPI's module supports two (of the four) standard SPI modes. These are Mode 0,0 and 1,1. The SPI mode is determined by the state of the SCK pin (VIH or VIL) on the when the CS pin transitions from inactive (VIH) to active (VIL or VIHH). All SPI interface signals are high-voltage tolerant.
Note 1: If high voltage commands are desired, some type of external circuitry needs to be implemented.
FIGURE 6-1:
Typical SPI Interface Block Diagram.
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6.1 SDI, SDO, SCK, and CS Operation
6.1.4 THE CS SIGNAL
The operation of the four SPI interface pins are discussed in this section. These pins are: * * * * SDI (Serial Data In) SDO (Serial Data Out) SCK (Serial Clock) CS (Chip Select) The Chip Select (CS) signal is used to select the device and frame a command sequence. To start a command, or sequence of commands, the CS signal must transition from the inactive state (VIH) to an active state (VIL or VIHH). After the CS signal has gone active, the SDO pin is driven and the clock bit counter is reset. Note: There is a required delay after the CS pin goes active to the 1st edge of the SCK pin.
The serial interface works on either 8-bit or 16-bit boundaries depending on the selected command. The Chip Select (CS) pin frames the SPI commands.
6.1.1
SERIAL DATA IN (SDI)
The Serial Data In (SDI) signal is the data signal into the device. The value on this pin is latched on the rising edge of the SCK signal.
If an error condition occurs for an SPI command, then the command byte's Command Error (CMDERR) bit (on the SDO pin) will be driven low (VIL). To exit the error condition, the user must take the CS pin to the VIH level. When the CS pin returns to the inactive state (VIH) the SPI module resets (including the Address Pointer). While the CS pin is in the inactive state (VIH), the serial interface is ignored. This allows the host controller to interface to other SPI devices using the same SDI, SDO and SCK signals. The CS pin has an internal pull-up resistor. The resistor is disabled when the voltage on the CS pin is at the VIL level. This means that when the CS pin is not driven, the internal pull-up resistor will pull this signal to the VIH level. When the CS pin is driven low (VIL), the resistance becomes very large to reduce the device current consumption. The high voltage capability of the CS pin allows High Voltage commands. Support of High Voltage commands allows circuit compatibility with the corresponding nonvolatile device.
6.1.2
SERIAL DATA OUT (SDO)
The Serial Data Out (SDO) signal is the data signal out of the device. The value on this pin is driven on the falling edge of the SCK signal. Once the CS pin is forced to the active level (VIL or VIHH), the SDO pin will be driven. The state of the SDO pin is determined by the serial bit's position in the command, the command selected, and if there is a command error state (CMDERR).
6.1.3
SERIAL CLOCK (SCK) (SPI FREQUENCY OF OPERATION)
The SPI interface is specified to operate up to 10 MHz. The actual clock rate depends on the configuration of the system and the serial command used. Table 6-1 shows the SCK frequency.
TABLE 6-1:
SCK FREQUENCY (1)
Command Write, Increment, Decrement 10 MHz
Memory Type Access
Read 10 MHz
Volatile Memory Note 1:
SDI, SDO
This is the maximum clock frequency without an external pull-up resistor.
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6.2 The SPI Modes
6.2.2 MODE 1,1
The SPI module supports two (of the four) standard SPI modes. These are Mode 0,0 and 1,1. The mode is determined by the state of the SDI pin on the rising edge of the 1st clock bit (of the 8-bit byte). In Mode 1,1: SCK Idle state = high (VIH), data is clocked in on the SDI pin on the rising edge of SCK and clocked out on the SDO pin on the falling edge of SCK.
6.2.1
MODE 0,0
6.3
SPI Waveforms
In Mode 0,0: SCK Idle state = low (VIL), data is clocked in on the SDI pin on the rising edge of SCK and clocked out on the SDO pin on the falling edge of SCK.
Figure 6-2 through Figure 6-5 show the different SPI command waveforms. Figure 6-2 and Figure 6-3 are read and write commands. Figure 6-4 and Figure 6-5 are Increment and Decrement commands. Support of High Voltage commands allows circuit compatibility with the corresponding nonvolatile device.
VIH CS SCK
VIHH VIL
Write to SSPBUF CMDERR bit SDO SDI Input Sample bit15 bit14 bit13 bit12 bit11 AD3 AD2 AD1 AD0 bit15 bit14 bit13 bit12 bit10 bit9 X bit9 bit8 D8 bit8 bit7 D7 bit7 bit6 D6 bit6 bit5 D5 bit5 bit4 D4 bit4 bit3 D3 bit3 bit2 bit1 bit0 D0 bit0
C1
C0
D2 D1 bit2 bit1
FIGURE 6-2:
VIHH VIL
16-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1).
VIH CS
SCK Write to SSPBUF SDO SDI Input Sample bit15 bit14 bit13 bit12 bit11
CMDERR bit bit10 bit9 X bit9 bit8 D8 bit8 bit7 D7 bit7 bit6 D6 bit6 bit5 D5 bit5 bit4 D4 bit4 bit3 D3 bit3 bit2 bit1 bit0 D0 bit0
AD3 AD2 AD1 AD0 bit15 bit14 bit13 bit12
C1
C0
D2 D1 bit2 bit1
FIGURE 6-3:
16-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0).
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MCP433X/435X
CS VIH VIHH VIL SCK
Write to SSPBUF CMDERR bit "1" = Valid Command "0" = Invalid Command SDO SDI bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
AD3 bit7
AD2
AD1
AD0
C1
C0
X
X bit0
Input Sample
FIGURE 6-4:
8-Bit Commands (Increment, Decrement) - SPI Waveform with PIC MCU (Mode 1,1).
VIHH VIL
VIH CS
SCK Write to SSPBUF
CMDERR bit "1" = Valid Command "0" = Invalid Command bit7 AD3 bit7 bit6 AD2 bit5 AD1 bit4 AD0 bit3 C1 bit2 C0 bit1 X bit0 X bit0
SDO SDI
Input Sample
FIGURE 6-5:
8-Bit Commands (Increment, Decrement) - SPI Waveform with PIC MCU (Mode 0,0).
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MCP433X/435X
7.0 DEVICE COMMANDS
7.1 Command Byte
The MCP43XX's SPI command format supports 16 memory address locations and four commands. Each command has two modes: * Normal Serial Commands * High-Voltage Serial Commands Normal serial commands are those where the CS pin is driven to VIL. With high-voltage serial commands, the CS pin is driven to VIHH. In each mode, there are four possible commands. These commands are shown in Table 7-1. The 8-bit commands (Increment Wiper and Decrement Wiper commands) contain a command byte, see Figure 7-1, while 16-bit commands (Read Data and Write Data commands) contain a command byte and a data byte. The command byte contains two data bits, see Figure 7-1. Table 7-2 shows the supported commands for each memory location and the corresponding values on the SDI and SDO pins. Table 7-3 shows an overview of all the SPI commands and their interaction with other device features. The command byte has three fields, the address, the command, and 2 data bits, see Figure 7-1. Currently only one of the data bits is defined (D8). This is for the Write command. The device memory is accessed when the master sends a proper command byte to select the desired operation. The memory location getting accessed is contained in the command byte's AD3:AD0 bits. The action desired is contained in the command byte's C1:C0 bits, see Table 7-1. C1:C0 determines if the desired memory location will be read, written, incremented (wiper setting +1) or decremented (wiper setting -1). The Increment and Decrement commands are only valid on the volatile wiper registers. As the command byte is being loaded into the device (on the SDI pin), the device's SDO pin is driving. The SDO pin will output high bits for the first six bits of that command. On the 7th bit, the SDO pin will output the CMDERR bit state (see Section 7.3 "Error Condition"). The 8th bit state depends on the command selected.
TABLE 7-1:
COMMAND BIT OVERVIEW
# of Bits 16-Bits 16-Bits 8-Bits 8-Bits Operates on Volatile/ Nonvolatile memory Both Both Volatile Only Volatile Only
C1:C0 Bit Command States 11 00 01 10 Read Data Write Data Increment Decrement
8-bit Command Command Byte AAAACCDD DDDD1098 3210 Memory Address Data Bits Command Bits
16-bit Command Command Byte Data Byte
AAAACCDDDDDDDDDD DDDD109876543210 3210 Memory Address Command Bits Data Bits
Command Bits CC 10 0 0 = Write Data 0 1 = INCR 1 0 = DECR 1 1 = Read Data
FIGURE 7-1:
General SPI Command Formats.
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TABLE 7-2:
Address Value 00h Function Volatile Wiper 0
MEMORY MAP AND THE SUPPORTED COMMANDS
Command Write Data Read Data Increment Wiper Decrement Wiper Data (10-bits) (1) nn nnnn nnnn nn nnnn nnnn -- -- nn nnnn nnnn nn nnnn nnnn -- -- -- -- nn nnnn nnnn nn nnnn nnnn -- nn nnnn nnnn nn nnnn nnnn -- -- nn nnnn nnnn nn nnnn nnnn -- -- -- -- nn nnnn nnnn nn nnnn nnnn -- SPI String (Binary) MOSI (SDI pin) 0000 00nn 0000 11nn 0000 0100 0000 1000 0001 00nn 0001 11nn 0001 0100 0001 1000 -- -- 0100 00nn 0100 11nn -- 0110 00nn 0110 11nn 0110 0100 0110 1000 0111 00nn 0111 11nn 0111 0100 0111 1000 -- -- 1010 00nn 1010 11nn -- MISO (SDO pin) (2) 1111 1111 nnnn nnnn nnnn nnnn 1111 1111 nnnn nnnn 1111 111n 1111 1111 1111 1111 nnnn nnnn 1111 1111 nnnn nnnn 1111 111n 1111 1111 1111 1111 -- -- nnnn nnnn 1111 1111 nnnn nnnn 1111 111n -- nnnn nnnn 1111 1111 nnnn nnnn 1111 111n 1111 1111 1111 1111 nnnn nnnn 1111 1111 nnnn nnnn 1111 111n 1111 1111 1111 1111 -- -- nnnn nnnn 1111 1111 nnnn nnnn 1111 111n -- 1111 1111 nnnn nnnn 1111 1111 nnnn nnnn 1111 1111 nnnn nnnn 1111 1111 nnnn nnnn 1111 1111 nnnn nnnn
01h
Volatile Wiper 1
Write Data Read Data Increment Wiper Decrement Wiper
02h 03h 04h
(3)
Reserved Reserved
None None
Volatile Write Data TCON 0 Register Read Data Reserved Volatile Wiper 2 None Write Data Read Data Increment Wiper Decrement Wiper
05h 06h
07h
Volatile Wiper 3
Write Data Read Data Increment Wiper Decrement Wiper
08h 09h 0Ah (3) 0Bh-0Fh Note 1: 2: 3:
Reserved Reserved
None None
Volatile Write Data TCON 1 Register Read Data Reserved None
The data memory is only 9-bits wide, so the MSb is ignored by the device. All these address/command combinations are valid, so the CMDERR bit is set. Any other address/command combination is a command error state and the CMDERR bit will be clear. Increment or Decrement commands are invalid for these addresses.
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7.2 Data Byte
7.3.1 ABORTING A TRANSMISSION
Only the Read command and the Write command use the data byte, see Figure 7-1. These commands concatenate the 8 bits of the data byte with the one data bit (D8) contained in the command byte to form 9-bits of data (D8:D0). The command byte format supports up to 9-bits of data so that the 8-bit resistor network can be set to full scale (100h or greater). This allows wiper connections to Terminal A and to Terminal B. The D9 bit is currently unused, and corresponds to the position on the SDO data of the CMDERR bit. All SPI transmissions must have the correct number of SCK pulses to be executed. The command is not executed until the complete number of clocks have been received. Some commands also require the CS pin to be forced inactive (VIH). If the CS pin is forced to the inactive state (VIH) the serial interface is reset. Partial commands are not executed. SPI is more susceptible to noise than other bus protocols. The most likely case is that this noise corrupts the value of the data being clocked into the MCP43XX or the SCK pin is injected with extra clock pulses. This may cause data to be corrupted in the device, or a command error to occur, since the address and command bits were not a valid combination. The extra SCK pulse will also cause the SPI data (SDI) and clock (SCK) to be out of sync. Forcing the CS pin to the inactive state (VIH) resets the serial interface. The SPI interface will ignore activity on the SDI and SCK pins until the CS pin transition to the active state is detected (VIH to VIL or VIH to VIHH). Note 1: When data is not being received by the MCP43XX, It is recommended that the CS pin be forced to the inactive level (VIL) 2: It is also recommended that long continuous command strings should be broken down into single commands or shorter continuous command strings. This reduces the probability of noise on the SCK pin corrupting the desired SPI commands.
7.3
Error Condition
The CMDERR bit indicates if the four address bits received (AD3:AD0) and the two command bits received (C1:C0) are a valid combination (see Table 4-2). The CMDERR bit is high if the combination is valid and low if the combination is invalid. The command error bit will also be low if a write to a nonvolatile address has been specified and another SPI command occurs before the CS pin is driven inactive (VIH). SPI commands that do not have a multiple of 8 clocks are ignored. Once an error condition has occurred, any following commands are ignored. All following SDO bits will be low until the CMDERR condition is cleared by forcing the CS pin to the inactive state (VIH).
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7.4 Continuous Commands
The device supports the ability to execute commands continuously. While the CS pin is in the active state (VIL or VIHH). Any sequence of valid commands may be received. The following example is a valid sequence of events: 1. 2. 3. 4. 5. 6. 7. CS pin driven active (VIL or VIHH). Read Command. Increment Command (Wiper 0). Increment Command (Wiper 0). Decrement Command (Wiper 1). Write Command (volatile memory). CS pin driven inactive (VIH). Note 1: It is recommended that while the CS pin is active, only one type of command should be issued. When changing commands, it is recommended to take the CS pin inactive then force it back to the active state. 2: It is also recommended that long command strings should be broken down into shorter command strings. This reduces the probability of noise on the SCK pin corrupting the desired SPI command string.
TABLE 7-3:
COMMANDS
Command Name # of Bits 16-Bits 16-Bits 8-Bits 8-Bits 16-Bits 16-Bits 8-Bits 8-Bits High Voltage (VIHH) on CS pin? -- -- -- -- Yes Yes Yes Yes
Write Data Read Data Increment Wiper Decrement Wiper High-Voltage Write Data High-Voltage Read Data High-Voltage Increment Wiper High-Voltage Decrement Wiper
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7.5 Write Data Normal and High Voltage
7.5.1 SINGLE WRITE TO VOLATILE MEMORY
The write operation requires that the CS pin be in the active state (VILor VIHH). Typically, the CS pin will be in the inactive state (VIH) and is driven to the active state (VIL). The 16-bit Write command (command byte and data byte) is then clocked in on the SCK and SDI pins. Once all 16 bits have been received, the specified volatile address is updated. A write will not occur if the write command isn't exactly 16 clocks pulses. This protects against system issues from corrupting the nonvolatile memory locations. Figure 6-2 and Figure 6-3 show possible waveforms for a single write. COMMAND BYTE A D 3 1 SDO 1 SDI A D 2 1 1 A D 1 1 1 A D 0 1 1 0 0 D 9 1 0 D 8 1 0 D 7 1 0 D 6 1 0 DATA BYTE D 5 1 0 D 4 1 0 D 3 1 0 D 2 1 0 D 1 1 0 D 0 1 Valid Address/Command combination 0 Invalid Address/Command combination (1)
The Write command is a 16-bit command. The format of the command is shown in Figure 7-2. A Write command to a volatile memory location changes that location after a properly formatted Write command (16-clock) have been received.
1 1
1 1
Note 1: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-2:
Write Command - SDI and SDO States.
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MCP433X/435X
7.5.2 CONTINUOUS WRITES TO VOLATILE MEMORY
Continuous writes are possible only when writing to the volatile memory registers (address 00h, 01h and 04h). Figure 7-3 shows the sequence for three continuous writes. The writes do not need to be to the same volatile memory address. COMMAND BYTE SDI SDO A D 3 1 A D 3 1 A D 3 1 A D 2 1 A D 2 1 A D 2 1 A D 1 1 A D 1 1 A D 1 1 A D 0 1 A D 0 1 A D 0 1 0 0 D9 D 8 1 1* 1 0 D9 D 8 1 1* 1 0 D9 D 8 1 1* 1 D 7 1 D 7 1 D 7 1 D 6 1 D 6 1 D 6 1 DATA BYTE D 5 1 D 5 1 D 5 1 D 4 1 D 4 1 D 4 1 D 3 1 D 3 1 D 3 1 D 2 1 D 2 1 D 2 1 D 1 1 D 1 1 D 1 1 D 0 1 D 0 1 D 0 1
1 0
1 0
1
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH).
FIGURE 7-3:
Continuous Write Sequence.
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MCP433X/435X
7.6 Read Data Normal and High Voltage
7.6.1 SINGLE READ
The read operation requires that the CS pin be in the active state (VILor VIHH). Typically, the CS pin will be in the inactive state (VIH) and is driven to the active state (VILor VIHH). The 16-bit Read command (command byte and data byte) is then clocked in on the SCK and SDI pins. The SDO pin starts driving data on the 7th bit (CMDERR bit) and the addressed data comes out on the 8th through 16th clocks. Figure 6-2 through Figure 6-3 show possible waveforms for a single read.
The Read command is a 16-bit command. The format of the command is shown in Figure 7-4. The first 6 bits of the Read command determine the address and the command. The 7th clock will output the CMDERR bit on the SDO pin. The remaining 9-clocks the device will transmit the 9 data bits (D8:D0) of the specified address (AD3:AD0). Figure 7-4 shows the SDI and SDO information for a Read command. COMMAND BYTE A D 3 1 1 A D 2 1 1 A D 1 1 1 A D 0 1 1 1 1 X X X X X DATA BYTE X X X
X
X
SDI SDO
1 1
1 1
1 0
D 8 0
D 7 0
D 6 0
D 5 0
D 4 0
D 3 0
D 2 0
D 1 0
D Valid Address/Command combination 0 0 Attempted Memory Read of Reserved Memory location
READ DATA
FIGURE 7-4:
Read Command - SDI and SDO States.
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7.6.2 CONTINUOUS READS
Continuous reads allow the devices memory to be read quickly. Continuous reads are possible to all memory locations. Figure 7-5 shows the sequence for three continuous reads. The reads do not need to be to the same memory address.
COMMAND BYTE A D 3 1 A D 2 1 A D 1 1 A D 0 1 1 1 X X X X
DATA BYTE X X X X X X
SDI SDO
1
1 1* D 8 1 X X
D 7 X
D 6 X
D 5 X
D 4 X
D 3 X
D 2 X
D 1 X
D 0 X
A D 3 1
A D 2 1
A D 1 1
A D 0 1
1
1
1 1* D 8 1 X X
D 7 X
D 6 X
D 5 X
D 4 X
D 3 X
D 2 X
D 1 X
D 0 X
A D 3 1
A D 2 1
A D 1 1
A D 0 1
1
1
1 1* D 8
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH).
FIGURE 7-5:
Continuous Read Sequence.
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MCP433X/435X
7.7 Increment Wiper Normal and High Voltage
7.7.1 SINGLE INCREMENT
The Increment command is an 8-bit command. The Increment command can only be issued to volatile memory locations. The format of the command is shown in Figure 7-6. An Increment command to the volatile memory location changes that location after a properly formatted command (8-clocks) have been received. Increment commands provide a quick and easy method to modify the value of the volatile wiper location by +1 with minimal overhead.
COMMAND BYTE (INCR COMMAND (n+1)) SDI
Typically, the CS pin starts at the inactive state (VIH), but may already be in the active state due to the completion of another command. Figure 6-4 through Figure 6-5 show possible waveforms for a single increment. The increment operation requires that the CS pin be in the active state (VILor VIHH). Typically, the CS pin will be in the inactive state (VIH) and is driven to the active state (VILor VIHH). The 8-bit Increment command (command byte) is then clocked in on the SDI pin by the SCK pins. The SDO pin drives the CMDERR bit on the 7th clock. The wiper value will increment up to 100h on 8-bit devices and 80h on 7-bit devices. After the wiper value has reached full scale (8-bit = 100h, 7-bit = 80h), the wiper value will not be incremented further. If the wiper register has a value between 101h and 1FFh, the Increment command is disabled. See Table 7-4 for additional information on the Increment command versus the current volatile wiper value. The increment operations only require the Increment command byte while the CS pin is active (VILor VIHH) for a single increment. After the wiper is incremented to the desired position, the CS pin should be forced to VIH to ensure that unexpected transitions on the SCK pin do not cause the wiper setting to change. Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired increment occurs.
A D 3 1 SDO 1
A D 2 1 1
A D 1 1 1
A D 0 1 1
0
1
X
X
1 1
1 1* 1 Note 1, 2 1 0 0 Note 1, 3
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination all following SDO bits will be low until the CMDERR condition is cleared. (the CS pin is forced to the inactive state). 4: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH).
TABLE 7-4:
Current Wiper Setting 7-bit Pot 3FFh 081h 080h 07Fh 041h 040h 03Fh 001h 000h 8-bit Pot 3FFh 101h 100h 0FFh 081 080h 07Fh 001 000h
INCREMENT OPERATION VS. VOLATILE WIPER VALUE
Wiper (W) Properties Reserved (Full Scale (W = A)) Full Scale (W = A) W=N W = N (Mid-scale) W=N Zero Scale (W = B) Yes Yes Increment Command Operates? No No
FIGURE 7-6: Increment Command - SDI and SDO States.
Note: Table 7-2 shows the valid addresses for the Increment Wiper command. Other addresses are invalid.
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MCP433X/435X
7.7.2 CONTINUOUS INCREMENTS
Continuous increments are possible only when writing to the volatile memory registers (address 00h, 01h, 06h and 07h). Figure 7-7 shows a continuous increment sequence for three continuous writes. The writes do not need to be to the same volatile memory address. When executing an continuous Increment commands, the selected wiper will be altered from n to n+1 for each Increment command received. The wiper value will increment up to 100h on 8-bit devices and 80h on 7-bit devices. After the wiper value has reached full scale (8-bit = 100h, 7-bit = 80h), the wiper value will not be incremented further. If the wiper register has a value between 101h and 1FFh, the Increment command is disabled. COMMAND BYTE (INCR COMMAND (n+1)) SDI A D 3 1 1 SDO 1 1 A D 2 1 1 1 1 A D 1 1 1 1 1 A D 0 1 1 1 1 0 1 X X Increment commands can be sent repeatedly without raising CS until a desired condition is met. When executing a continuous command string, the Increment command can be followed by any other valid command. The wiper terminal will move after the command has been received (8th clock). After the wiper is incremented to the desired position, the CS pin should be forced to VIH to ensure that unexpected transitions (on the SCK pin do not cause the wiper setting to change). Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired increment occurs.
COMMAND BYTE (INCR COMMAND (n+2)) A D 3 1 0 1 1 A D 2 1 0 1 1 A D 1 1 0 1 1 A D 0 1 0 1 1 0 1 X X
COMMAND BYTE (INCR COMMAND (n+3)) A D 3 1 0 0 1 A D 2 1 0 0 1 A D 1 1 0 0 1 A D 0 1 0 0 1 0 1 X X
1 1 1 1
1 1* 1 100 111 111
1 0 1 1
1 1* 1 000 100 111
1 0 0 1
1 1* 1 Note 1, 2 0 0 0 Note 3, 4 0 0 0 Note 3, 4 1 0 0 Note 3, 4
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination. 4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-7:
Continuous Increment Command - SDI and SDO States.
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7.8 Decrement Wiper Normal and High Voltage
7.8.1 SINGLE DECREMENT
The Decrement command is an 8-bit command. The Decrement command can only be issued to volatile memory locations. The format of the command is shown in Figure 7-6. A Decrement command to the volatile memory location changes that location after a properly formatted command (8 clocks) have been received. Decrement commands provide a quick and easy method to modify the value of the volatile wiper location by -1 with minimal overhead. COMMAND BYTE (DECR COMMAND (n+1)) SDI A D 3 1 SDO 1 A D 2 1 1 A D 1 1 1 A D 0 1 1 1 0 X X Typically, the CS pin starts at the inactive state (VIH), but may already be in the active state due to the completion of another command. Figure 6-4 through Figure 6-5 show possible waveforms for a single decrement. The decrement operation requires that the CS pin be in the active state (VILor VIHH). Typically, the CS pin will be in the inactive state (VIH) and is driven to the active state (VILor VIHH). Then the 8-bit Decrement command (command byte) is clocked in on the SDI pin by the SCK pins. The SDO pin drives the CMDERR bit on the 7th clock. The wiper value will decrement from the wiper's full scale value (100h on 8-bit devices and 80h on 7-bit devices). Above the wiper's full scale value (8-bit = 101h to 1FFh, 7-bit = 81h to FFh), the Decrement command is disabled. If the wiper register has a zero scale value (000h), then the wiper value will not decrement. See Table 7-5 for additional information on the Decrement command vs. the current volatile wiper value. The Decrement commands only require the Decrement command byte, while the CS pin is active (VILor VIHH) for a single decrement. After the wiper is decremented to the desired position, the CS pin should be forced to VIH to ensure that unexpected transitions on the SCK pin do not cause the wiper setting to change. Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired decrement occurs.
1 1
1 1* 1 Note 1, 2 1 0 0 Note 1, 3
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination all following SDO bits will be low until the CMDERR condition is cleared. (the CS pin is forced to the inactive state). 4: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH).
TABLE 7-5:
Current Wiper Setting 7-bit Pot 3FFh 081h 080h 07Fh 041h 040h 03Fh 001h 000h 8-bit Pot 3FFh 101h 100h 0FFh 081 080h 07Fh 001 000h
DECREMENT OPERATION VS. VOLATILE WIPER VALUE
Wiper (W) Properties Reserved (Full Scale (W = A)) Full Scale (W = A) W=N W = N (Mid-scale) W=N Zero Scale (W = B) No Yes Decrement Command Operates? No Yes
FIGURE 7-8: Decrement Command - SDI and SDO States.
Note: Table 7-2 shows the valid addresses for the Decrement Wiper command. Other addresses are invalid.
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7.8.2 CONTINUOUS DECREMENTS
Continuous decrements are possible only when writing to the volatile memory registers (address 00h, 01h, and 04h). Figure 7-9 shows a continuous decrement sequence for three continuous writes. The writes do not need to be to the same volatile memory address. When executing continuous Decrement commands, the selected wiper will be altered from n to n-1 for each Decrement command received. The wiper value will decrement from the wiper's full scale value (100h on 8-bit devices and 80h on 7-bit devices). Above the wiper's full scale value (8-bit = 101h to 1FFh, 7-bit = 81h to FFh), the Decrement command is disabled. If the Wiper register has a zero scale value (000h), then the wiper value will not decrement. See Table 7-5 for additional information on the Decrement command vs. the current volatile wiper value. COMMAND BYTE (DECR COMMAND (n-1)) SDI A D 3 1 1 SDO 1 1 A D 2 1 1 1 1 A D 1 1 1 1 1 A D 0 1 1 1 1 1 0 X X Decrement commands can be sent repeatedly without raising CS until a desired condition is met. When executing a continuous command string, the Decrement command can be followed by any other valid command. The wiper terminal will move after the command has been received (8th clock). After the wiper is decremented to the desired position, the CS pin should be forced to VIH to ensure that "unexpected" transitions (on the SCK pin do not cause the wiper setting to change). Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired decrement occurs.
COMMAND BYTE (DECR COMMAND (n-1)) A D 3 1 0 1 1 A D 2 1 0 1 1 A D 1 1 0 1 1 A D 0 1 0 1 1 1 0 X X
COMMAND BYTE (DECR COMMAND (n-1)) A D 3 1 0 0 1 A D 2 1 0 0 1 A D 1 1 0 0 1 A D 0 1 0 0 1 1 0 X X
1 1 1 1
1 1* 1 100 111 111
1 0 1 1
1 1* 1 000 100 111
1 0 0 1
1 1* 1 Note 1, 2 0 0 0 Note 3, 4 0 0 0 Note 3, 4 1 0 0 Note 3, 4
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination. 4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-9:
Continuous Decrement Command - SDI and SDO States.
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MCP433X/435X
8.0 APPLICATIONS EXAMPLES
5V Voltage Regulator PIC(R) MCU SDI CS SCK I/O SDO 3V Digital potentiometers have a multitude of practical uses in modern electronic circuits. The most popular uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. The MCP433X/435X devices can be used to replace the common mechanical trim pot in applications where the operating and terminal voltages are within CMOS process limitations (VDD = 2.7V to 5.5V).
MCP4XXX SDI CS SCK RESET SDO
8.1
Split Rail Applications
All inputs that would be used to interface to a host controller support high voltage on their input pin. This allows the MCP43XX device to be used in split power rail applications. An example of this is a battery application where the PIC(R) MCU is directly powered by the battery supply (4.8V) and the MCP43XX device is powered by the 3.3V regulated voltage. For SPI applications, these inputs are: * * * * CS SCK SDI (or SDI/SDO) RESET
FIGURE 8-1: System 1.
Voltage Regulator 3V PIC(R) MCU SDI CS SCK I/O SDO
Example Split Rail
5V
MCP4XXX SDI CS SCK RESET SDO
Figure 8-1 through Figure 8-2 show three example split rail systems. In this system, the MCP43XX interface input signals need to be able to support the PIC MCU output high voltage (VOH). In Example #1 (Figure 8-1), the MCP43XX interface input signals need to be able to support the PIC MCU output high voltage (VOH). If the split rail voltage delta becomes too large, then the customer may be required to do some level shifting due to MCP43XX VOH levels related to host controller VIH levels. In Example #2 (Figure 8-2), the MCP43XX interface input signals need to be able to support the lower voltage of the PIC MCU output high voltage level (VOH). Table 8-1 shows an example PIC microcontroller I/O voltage specifications and the MCP43XX specifications. So this PIC MCU operating at 3.3V will drive a VOH at 2.64V, and for the MCP43XX operating at 5.5V, the VIH is 2.47V. Therefore, the interface signals meet specifications.
FIGURE 8-2: System 2. TABLE 8-1:
PIC(R) MCU (1) VDD 5.5 5.0 4.5 3.3 3.0 2.7 VIH 4.4 4.0 3.6 2.4
Example Split Rail VOH - VIH COMPARISONS
MCP4XXX (2) VIH 1.35 VOH -- (3) 1.215 -- (3) 1.485 -- (3) 2.025 -- (3) 2.25 -- (3) 2.475 -- (3) VOH VDD Comment
4.4 4.0 3.6 2.4
2.7 3.0 3.3 5.0
2.64 2.64 4.5 2.16 2.16 5.5
Note 1:
2:
3:
VOH minimum = 0.8 * VDD; VOL maximum = 0.6V VIH minimum = 0.8 * VDD; VIL maximum = 0.2 * VDD; VOH minimum (SDA only) =; VOL maximum = 0.2 * VDD VIH minimum = 0.45 * VDD; VIL maximum = 0.2 * VDD The only MCP4XXX output pin is SDO, which is open-drain (or open-drain with internal pull-up) with high voltage support
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8.2 Techniques to Force the CS Pin to VIHH
PIC10F206 GP0 MCP4XXX GP2 C1 CS C2 R1
The circuit in Figure 8-3 shows a method using the TC1240A doubling charge pump. When the SHDN pin is high, the TC1240A is off, and the level on the CS pin is controlled by the PIC(R) microcontrollers (MCUs) IO2 pin. When the SHDN pin is low, the TC1240A is on and the VOUT voltage is 2 * VDD. The resistor R1 allows the CS pin to go higher than the voltage such that the PIC MCU's IO2 pin "clamps" at approximately VDD. TC1240A C+ VIN CSHDN VOUT R1 C2 MCP4XXX CS
PIC(R) MCU IO1
FIGURE 8-4: MCP4XXX Nonvolatile Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the VIHH voltage.
C1
8.3
Using Shutdown Modes
IO2
FIGURE 8-3: Using the TC1240A to Generate the VIHH Voltage.
The circuit in Figure 8-4 shows the method used on the MCP402X Nonvolatile Digital Potentiometer Evaluation Board (Part Number: MCP402XEV). This method requires that the system voltage be approximately 5V. This ensures that when the PIC10F206 enters a brown-out condition, there is an insufficient voltage level on the CS pin to change the stored value of the wiper. The "MCP402X Nonvolatile Digital Potentiometer Evaluation Board User's Guide" (DS51546) contains a complete schematic. GP0 is a general purpose I/O pin, while GP2 can either be a general purpose I/O pin or it can output the internal clock. For the serial commands, configure the GP2 pin as an input (high-impedance). The output state of the GP0 pin will determine the voltage on the CS pin (VIL or VIH). For high-voltage serial commands, force the GP0 output pin to output a high level (VOH) and configure the GP2 pin to output the internal clock. This will form a charge pump and increase the voltage on the CS pin (when the system voltage is approximately 5V).
Figure 8-5 shows a possible application circuit where the independent terminals could be used. Disconnecting the wiper allows the transistor input to be taken to the bias voltage level (disconnecting A and or B may be desired to reduce system current). Disconnecting Terminal A modifies the transistor input by the RBW rheostat value to the Common B. Disconnecting Terminal B modifies the transistor input by the RAW rheostat value to the Common A. The Common A and Common B connections could be connected to VDD and VSS.
Common A
Input A
W
To base of Transistor (or Amplifier)
B Input
Common B Balance Bias
FIGURE 8-5: Example Application Circuit using Terminal Disconnects.
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MCP433X/435X
8.4 Design Considerations
8.4.2 LAYOUT CONSIDERATIONS
In the design of a system with the MCP43XX devices, the following considerations should be taken into account: * Power Supply Considerations * Layout Considerations Several layout considerations may be applicable to your application. These may include: * Noise * Footprint Compatibility * PCB Area Requirements
8.4.1
POWER SUPPLY CONSIDERATIONS
8.4.2.1
Noise
The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-6 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 F. This capacitor should be placed as close (within 4 mm) to the device power pin (VDD) as possible. The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and VSS should reside on the analog plane. VDD 0.1 F VDD 0.1 F PIC(R) Microcontroller
Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP43XX's performance. Careful board layout minimizes these effects and increases the Signal-to-Noise Ratio (SNR). Multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. If low noise is desired, breadboards and wire-wrapped boards are not recommended.
8.4.2.2
Footprint Compatibility
The specification of the MCP43XX pinouts was done to allow systems to be designed to easily support the use of either the dual (MCP42XX) or quad (MCP43XX) device. Figure 8-7 shows how the dual pinout devices fit on the quad device footprint. For the Rheostat devices, the dual device is in the MSOP package, so the footprints would need to be offset from each other. MCP43X1 Quad Potentiometers
P3A P3W P3B CS SCK SDI VSS P1B P1W P1A
A W
MCP433X/435X
U/D
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 12 12 11
P2A P2W P2B VDD SDO RESET WP P0B P0W P0A
MCP42X1 Pinout (1)
B
CS
P3W P3B CS SCK SDI VSS P1B
TSSOP MCP43X2 Quad Rheostat 1 2 3 4 5 6 7 14 13 12 11 10 9 8
P2W P2B VDD SDO P0B P0W P1W
VSS
VSS
MCP42X2 Pinout
FIGURE 8-6: Connections.
Typical Microcontroller
TSSOP Note 1: Pin 15 (RESET) is the Shutdown (SHDN) pin on the MCP42x1 device.
FIGURE 8-7: Quad Pinout (TSSOP Package) vs. Dual Pinout.
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Figure 8-8 shows possible layout implementations for an application to support the quad and dual options on the same PCB.
8.4.2.3
PCB Area Requirements
Potentiometers Devices
MCP43X1 MCP42X1
In some applications, PCB area is a criteria for device selection. Table 8-2 shows the package dimensions and area for the different package options. The table also shows the relative area factor compared to the smallest area. For space critical applications, the QFN package would be the suggested package.
TABLE 8-2:
Package
PACKAGE FOOTPRINT (1)
Package Footprint Area (mm2) 32.64 16.00 42.24 Dimensions (mm) Relative Area 2.04 1 2.64
Pins
Type
Code X Y 6.40 4.00 6.40
Rheostat Devices
MCP42X2 MCP43X2
14 20
TSSOP QFN TSSOP
ST ML ST
5.10 4.00 6.60
Note 1: Does not include recommended land pattern dimensions.
8.4.3 FIGURE 8-8: Dual Devices. Layout to support Quad and
RESISTOR TEMPCO
Characterization curves of the resistor temperature coefficient (Tempco) are shown in Figure 2-11, Figure 2-32, Figure 2-52, and Figure 2-72. These curves show that the resistor network is designed to correct for the change in resistance as temperature increases. This technique reduces the end to end change is RAB resistance.
8.4.4
HIGH VOLTAGE TOLERANT PINS
High voltage support (VIHH) on the Serial Interface pins supports in-circuit accommodation of split rail applications and power supply sync issues.
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MCP433X/435X
9.0
9.1
DEVELOPMENT SUPPORT
Development Tools
9.2
Technical Documentation
Several development tools are available to assist in your design and evaluation of the MCP43XX devices. The currently available tools are shown in Table 9-1. These boards may be purchased directly from the Microchip web site at www.microchip.com.
Several additional technical documents are available to assist you in your design and development. These technical documents include Application Notes, Technical Briefs, and Design Guides. Table 9-2 shows some of these documents.
TABLE 9-1:
Board Name
DEVELOPMENT TOOLS
Part # TSSOP20EV MCP43XXEV Supported Devices MCP43XX MCP4361 MCP42XX MCP42XXX, MCP42XX, MCP4021 and MCP4011
20-pin TSSOP and SSOP Evaluation Board MCP4361 Evaluation Board (1)
MCP42XX Digital Potentiometer PICtailTM Plus Demo MCP42XXDM-PTPLS Board MCP4XXX Digital Potentiometer Daughter Board (2) MCP4XXXDM-DB
Note 1: This Evaluation Board is planned to be available by March 2010. This board uses the TSSOP20EV PCB and requires the PICkitTM Serial Analyzer (see User's Guide for details). This kit also includes 1 blank TSSOP20EV PCB. 2: Requires the use of a PICDEMTM Demo board (see User's Guide for details).
TABLE 9-2:
Application Note Number AN1080 AN737 AN692 AN691 AN219 -- --
TECHNICAL DOCUMENTATION
Title Understanding Digital Potentiometers Resistor Variations Using Digital Potentiometers to Design Low-Pass Adjustable Filters Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect Optimizing the Digital Potentiometer in Precision Circuits Comparing Digital Potentiometers to Mechanical Potentiometers Digital Potentiometer Design Guide Signal Chain Design Guide Literature # DS01080 DS00737 DS00692 DS00691 DS00219 DS22017 DS21825
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NOTES:
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10.0
10.1
PACKAGING INFORMATION
Package Marking Information
14-Lead TSSOP Example
XXXXXXXX YYWW NNN
4352502E 1004 256
20-Lead QFN (4x4) XXXXX XXXXXX XXXXXX YYWWNNN
Example 4351 502EML e3 ^^ 1004 256
20-Lead TSSOP
Example
XXXXXXXX XXXXX NNN YYWW
4351502 EST ^^ 256 e3 1004
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
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MCP433X/435X
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Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
2010 Microchip Technology Inc.
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2010 Microchip Technology Inc.
MCP433X/435X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
2010 Microchip Technology Inc.
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NOTES:
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APPENDIX A: REVISION HISTORY
Revision A (March 2010)
* Original Release of this Document. Note: Original TSSOP-20 device samples used the example marking shown in Figure A-1. Future device samples will usE the part marking shown in Section 10. Figure A-1: Old example TSSOP-20 device marking.
Example
MCP4351
e3 EST ^^ 256 1004
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NOTES:
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APPENDIX B: CHARACTERIZATION DATA ANALYSIS
B.1 Low-Voltage Operation
This appendix gives an overview of CMOS semiconductor characteristics at lower voltages. This is important so that the 1.8V resistor network characterization graphs of the MCP433X/435X devices can be better understood. For this discussion, we will use the 5 k device data. This data was chosen since the variations of wiper resistance has much greater implications for devices with smaller RAB resistances. Figure B-1 shows the worst case RBW error from the average RBW as a percentage, while Figure B-2 shows the RBW resistance verse wiper code graph. Nonlinear behavior occurs at approximately wiper code 160. This is better shown in Figure B-2, where the RBW resistance changes from a linear slope. This change is due to the change in the wiper resistance.
2.00% 1.00% 0.00% -1.00%
Some designers may desire to understand the device operational characteristics outside of the specified operating conditions of the device. Applications where the knowledge of the resistor network characteristics could be useful include battery powered devices and applications that experience brown-out conditions. In battery applications the application voltage decays over time until new batteries are installed. As the voltage decays, the system will continue to operate. At some voltage level, the application will be below its specified operating voltage range. This is dependent on the individual components used in the design. It is still useful to understand the device characteristics to expect when this low-voltage range is encountered. Unlike a microcontroller which can use an external supervisor device to force the controller into the Reset state, a digital potentiometer's resistance characteristic is not specified. But understanding the operational characteristics can be important in the design of the applications circuit for this low-voltage condition. Other application system scenarios where understanding the low-voltage characteristics of the resistor network could be important is for system brown out conditions. For the MCP433X/435X devices, the analog operation is specified at a minimum of 2.7V. Device testing has Terminal A connected to the device VDD (for potentiometer configuration only) and Terminal B connected to VSS.
Error %
-2.00% -3.00% -4.00% -5.00% -6.00% -7.00% 0 32 64 96 128 160 192
-40C +25C +85C +125C
224 256
Wiper Code
FIGURE B-1: 1.8V Worst Case RBW Error from Average RBW (RBW0-RBW3) vs. Wiper Code and Temperature (VDD = 1.8V, IW = 190 A).
7000 6000 Resistance () 5000 4000 3000 2000 1000 0 0 32 64 96 128 160 Wiper Code 192 224 256 -40C +25C +85C +125C
FIGURE B-2: RBW vs. Wiper Code And Temperature (VDD = 1.8V, IW = 190 A).
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Figure B-3 and Figure B-4 show the wiper resistance for VDD voltages of 5.5, 3.0, 1.8 Volts. These graphs show that as the resistor ladder wiper node voltage (VWCn) approaches the VDD/2 voltage, the wiper resistance increases. These graphs also show the different resistance characteristics of the NMOS and PMOS transistors that make up the wiper switch. This is demonstrated by the wiper code resistance curve, which does not mirror itself around the mid-scale code (wiper code = 128). So why is the RW graphs showing the maximum resistance at about mid-scale (wiper code = 128) and the RBW graphs showing the issue at code 160? This requires understanding low-voltage transistor characteristics as well as how the data was measured.
220 200 180 Resistance () 160 140 120 100 80 60 40 20 0 64 128 Wiper Code 192 256
The method in which the data was collected is important to understand. Figure B-5 shows the technique that was used to measure the RBW and RW resistance. In this technique Terminal A is floating and Terminal B is connected to ground. A fixed current is then forced into the wiper (IW) and the corresponding wiper voltage (VW) is measured. Forcing a known current through RBW (IW) and then measuring the voltage difference between the wiper (VW) and Terminal A (VA), the wiper resistance (RW) can be calculated, see Figure B-5. Changes in IW current will change the wiper voltage (VW). This may effect the device's wiper resistance (RW). floating VA A W IW B VB RBW = VW/IW RW = (VW-VA)/IW
VW
-40C @ 3.0V -40C @5.5V
+25C @ 3.0V +25C @ 5.5V
+85C @ 3.0V +85C @ 5.5V
+125C @ 3.0V +125C @ 5.5V
FIGURE B-5:
RBW and RW Measurement.
FIGURE B-3: Wiper Resistance (RW) vs. Wiper Code and Temperature (VDD = 5.5V, IW = 900 UA; VDD = 3.0V, IW = 480 A).
Figure B-6 shows a block diagram of the resistor network where the RAB resistor is a series of 256 RS resistors. These resistors are polysilicon devices. Each wiper switch is an analog switch made up of an NMOS and PMOS transistor. A more detailed figure of the wiper switch is shown in Figure B-7. The wiper resistance is influenced by the voltage on the wiper switches nodes (VG, VW and VWCn). Temperature also influences the characteristics of the wiper switch, see Figure B-4. The NMOS transistor and PMOS transistor have different characteristics. These characteristics as well as the wiper switch node voltages determine the RW resistance at each wiper code. The variation of each wiper switch's characteristics in the resistor network is greater then the variation of the RS resistors. The voltage on the resistor network node (VWCn) is dependent upon the wiper code selected and the voltages applied to VA, VB and VW. The wiper switch VG voltage to VW or VWCn voltage determines how strongly the transistor is turned on. When the transistor is weakly turned on the wiper resistance RW will be high. When the transistor is strongly turned on, the wiper resistance (RW) will be in the typical range.
2020 1520 1020 520 20 0
-40C @ 1.8V +25C @ 1.8V +85C @ 1.8V +125C @ 1.8V
Resistance ()
64
128 Wiper Code
192
256
FIGURE B-4: Wiper Resistance (RW) vs. Wiper Code and Temperature (VDD = 1.8V, IW = 260 A).
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A
VA
Nn RS Nn-1 RS Nn-2 RAB Nn-3 RS So looking at the wiper voltage (VW) for the 3.0V and 1.8V data gives the graphs in Figure B-8 and Figure B-9. In the 1.8V graph, as the VW approaches 0.8V, the voltage increases nonlinearly. Since V = I * R, and the current (IW) is constant, it means that the device resistance increased nonlinearly at around wiper code 160.
RW (1)
RW (1)
DVG
Wiper Voltage (V)
1.2 1.0 0.8 0.6 0.4 0.2 0.0
-40C +25C +85C +125C
VWC(n-2)
NMOS PMOS
RW (1)
VW
N1 RS N0 RW RW
(1)
W
0
32
64
96 128 160 Wiper Code
192
224
256
(1)
FIGURE B-8: Wiper Voltage (VW) vs. Wiper Code (VDD = 3.0V, IW = 190 A).
1.4 1.2 Wiper Voltage (V)
B
Note 1:
VB
The wiper resistance is dependent on several factors including, wiper code, device VDD, Terminal voltages (on A, B and W), and temperature.
1.0 0.8 0.6 0.4 0.2 0.0 0 32 64 96 128 160 Wiper Code 192
-40C +25C +85C +125C
FIGURE B-6: Diagram.
Resistor Network Block
The characteristics of the wiper is determined by the characteristics of the wiper switch at each of the resistor networks tap points. Figure B-7 shows an example of a wiper switch. As the device operational voltage becomes lower, the characteristics of the wiper switch change due to a lower voltage on the VG signal. Figure B-7 shows an implementation of a wiper switch. When the transistor is turned off, the switch resistance is in the Giga s. When the transistor is turned on, the switch resistance is dependent on the VG, VW and VWCn voltages. This resistance is referred to as RW. RW (1) "gate" NWC VWCn "gate" Note 1: Wiper Resistance (RW) depends on the voltages at the wiper switch nodes (VG, VW and VWCn).
NMOS PMOS
224
256
FIGURE B-9: Wiper Voltage (VW) vs. Wiper Code (VDD = 1.8V, IW = 190 A).
VG (VDD/VSS)
Wiper VW
FIGURE B-7:
Wiper Switch.
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Using the simulation models of the NMOS and PMOS devices for the MCP43XX analog switch (Figure B-10), we plot the device resistance when the devices are turned on. Figure B-11 and Figure B-12 show the resistances of the NMOS and PMOS devices as the VIN voltage is increased. The wiper resistance (RW) is simply the parallel resistance on the NMOS and PMOS devices (RW = RNMOS || RPMOS). Below the threshold voltage for the NMOS ad PMOS devices, the resistance becomes very large (Giga s). In the transistors active region, the resistance is much lower. For these graphs, the resistances are on different scales. Figure B-13 and Figure B-14 only plots the NMOS and PMOS device resistance for their active region and the resulting wiper resistance. For these graphs, all resistances are on the same scale. RW "gate" VIN "gate"
NMOS PMOS
7.00E+09 NMOS and PMOS Resistance () 6.00E+09 5.00E+09 4.00E+09 3.00E+09 2.00E+09 1.00E+09 0.00E+00 0.0 0.6 1.2 1.8 VIN Voltage 2.4 3.0
NMOS PMOS Theshold Theshold RPMOS RW RNMOS
160 140 120 100 80 60 40 20 0 Wiper Resistance ()
FIGURE B-12: NMOS and PMOS Transistor Resistance (RNMOS, RPMOS) and Wiper Resistance (RW) VS. VIN (VDD = 1.8V).
300
VG (VDD/VSS) VOUT
Resistance () 250 200 150 100 50
RNMOS
RPMOS
FIGURE B-10:
3.00E+10 NMOS and PMOS Resistance () 2.50E+10
RPMOS
Analog Switch.
2500
RW
RW
RNMOS
0 Wiper Resistance () 2000 1500 1000 0.0 0.6 1.2 1.8 VIN Voltage 2.4 3.0
2.00E+10 1.50E+10 1.00E+10 5.00E+09 0.00E+00 0.0 0.3 0.6 0.9 1.2 VIN Voltage 1.5 1.8
PMOS Theshold
NMOS 500 Theshold
0
FIGURE B-13: NMOS and PMOS Transistor Resistance (RNMOS, RPMOS) and Wiper Resistance (RW) VS. VIN (VDD = 3.0V).
5000 4500 4000 Resistance () 3500 3000 2500 2000 1500 1000 500 0 0.0 0.3 0.6 0.9 1.2 VIN Voltage 1.5 1.8
RNMOS RPMOS RW
FIGURE B-11: NMOS and PMOS Transistor Resistance (RNMOS, RPMOS) and Wiper Resistance (RW) VS. VIN (VDD = 3.0V).
FIGURE B-14: NMOS and PMOS Transistor Resistance (RNMOS, RPMOS) and Wiper Resistance (RW) VS. VIN (VDD = 1.8V).
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B.2 Optimizing Circuit Design for LowVoltage Characteristics
R1 A VA VW W VOUT
The low-voltage nonlinear characteristics can be minimized by application design. The section will show two application circuits that can be used to control a programmable reference voltage (VOUT). Minimizing the low-voltage nonlinear characteristics is done by keeping the voltages on the wiper switch nodes at a voltage where either the NMOS or PMOS transistor is turned on. An example of this is if we are using a digital potentiometer for a voltage reference (VOUT). Lets say that we want VOUT to range from 0.5 * VDD to 0.6 * VDD. In example implementation #1 (Figure B-15) we window the digital potentiometer using resistors R1 and R2. When the wiper code is at full scale the VOUT voltage will be 0.6 * VDD, and when the wiper code is at zero scale the VOUT voltage will be 0.5 * VDD. Remember that the digital potentiometers RAB variation must be included. Table B-1 shows that the VOUT voltage can be selected to be between 0.455 * VDD and 0.727 * VDD, which includes the desired range. With respect to the voltages on the resistor network node, at 1.8V the VA voltage would range from 1.29V to 1.31V while the VB voltage would range from 0.82V to 0.86V. These voltages cause the wiper resistance to be in the nonlinear region (see Figure B-12). In Potentiometer mode, the variation of the wiper resistance is typically not an issue, as shown by the INL/DNL graph (Figure 2-7). In example implementation #2 (Figure B-16) we use the digital potentiometer in Rheostat mode. The resistor ladder uses resistors R1 and R2 with RBW at the bottom of the ladder. When the wiper code is at full scale, the VOUT voltage will be 0.6 * VDD and when the wiper code is at full scale the VOUT voltage will be 0.5 * VDD. Remember that the digital potentiometers RAB variation must be included. Table B-2 shows that the VOUT voltage can be selected to be between 0.50 * VDD and 0.687 * VDD, which includes the desired range. With respect to the voltages on the resistor network node, at 1.8V the VW voltage would range from 0.29V to 0.38V. These voltages cause the wiper resistance to be in the linear region (see Figure B-12).
B R2
VB
FIGURE B-15: TABLE B-1:
Example Implementation #1. EXAMPLE #1 VOLTAGE CALCULATIONS
Variation Min Typ 12,000 20,000 10,000 0.70 VDD 0.50 VDD 0.70 VDD 0.50 VDD Max 12,000 20,000 12,000 0.727 VDD 0.455 VDD 0.727 VDD 0.455 VDD
R1 R2 RAB
12,000 20,000 8,000
VOUT (@ FS) 0.714 VDD VOUT (@ ZS) 0.476 VDD VA VB 0.714 VDD 0.476 VDD
Legend: FS - Full Scale, ZS - Zero Scale
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R1 VOUT R2 A VA W VW
B
VB
FIGURE B-16: TABLE B-2:
Example Implementation #2. EXAMPLE #2 VOLTAGE CALCULATIONS
Variation Min Typ 10,000 10,000 10,000 0.643 VDD 0.50 VDD 0.286 VDD VSS Max 10,000 10,000 12,000 0.687 VDD 0.50 VDD 0.375 VDD VSS
R1 R2 RBW (max)
10,000 10,000 8,000
VOUT (@ FS) 0.667 VDD VOUT(@ ZS) 0.50 VDD VW (@ FS) VW (@ ZS) 0.333 VDD VSS
Legend: FS - Full Scale, ZS - Zero Scale
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PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -XXX Resistance Version X Temperature Range /XX Package
Examples:
a) b) c) d) e) f) g) h) a) b) c) d) e) f) g) h) a) b) c) d) e) f) g) h) a) b) c) d) e) f) g) h) XX MCP4331-502E/XX: MCP4331T-502E/XX: MCP4331-103E/XX: MCP4331T-103E/XX: MCP4331-503E/XX: MCP4331T-503E/XX: MCP4331-104E/XX: MCP4331T-104E/XX: MCP4332-502E/XX: MCP4332T-502E/XX: MCP4332-103E/XX: MCP4332T-103E/XX: MCP4332-503E/XX: MCP4332T-503E/XX: MCP4332-104E/XX: MCP4332T-104E/XX: MCP4351-502E/XX: MCP4351T-502E/XX: MCP4351-103E/XX: MCP4351T-103E/XX: MCP4351-503E/XX: MCP4351T-503E/XX: MCP4351-104E/XX: MCP4351T-104E/XX: MCP4352-502E/XX: MCP4352T-502E/XX: MCP4352-103E/XX: MCP4352T-103E/XX: MCP4352-503E/XX: MCP4352T-503E/XX: MCP4352-104E/XX: MCP4352T-104E/XX: 5 k 20-LD Device T/R, 5 k20-LD Device 10 k, 20-LD Device T/R, 10 k, 20-LD Device 50 k, 20-LD Device T/R, 50 k, 20-LD Device 100 k, 20-LD Device T/R, 100 k, 20-LD Device 5 k 14-LD Device T/R, 5 k14-LD Device 10 k, 14-LD Device T/R, 10 k, 14-LD Device 50 k, 8LD Device T/R, 50 k, 14-LD Device 100 k, 14-LD Device T/R, 100 k, 14-LD Device 5 k 20-LD Device T/R, 5 k20-LD Device 10 k, 20-LD Device T/R, 10 k, 20-LD Device 50 k, 20-LD Device T/R, 50 k, 20-LD Device 100 k, 20-LD Device T/R, 100 k, 20-LD Device 5 k 14-LD Device T/R, 5 k14-LD Device 10 k, 14-LD Device T/R, 10 k, 14-LD Device 50 k, 14-LD Device T/R, 50 k, 14-LD Device 100 k, 14-LD Device T/R, 100 k, 14-LD Device
Device:
MCP4331: MCP4331T: MCP4332: MCP4332T: MCP4351: MCP4351T: MCP4352: MCP4352T:
Quad Volatile 7-bit Potentiometer Quad Volatile 7-bit Potentiometer (Tape and Reel) Quad Volatile 7-bit Rheostat Quad Volatile 7-bit Rheostat (Tape and Reel) Quad Volatile 8-bit Potentiometer Quad Volatile 8-bit Potentiometer (Tape and Reel) Quad Volatile 8-bit Rheostat Quad Volatile 8-bit Rheostat (Tape and Reel)
Resistance Version:
502 103 503 104 E
= = = =
5 k 10 k 50 k 100 k
Temperature Range: Package:
= -40C to +125C (Extended)
= Plastic Thin Shrink Small Outline (TSSOP), 14/20-lead ML = Plastic Quad Flat No-lead (4x4 QFN), 20-lead
ST
= ST for 14/20-lead TSSOP = ML for 20-lead QFN
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Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-061-4
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
2010 Microchip Technology Inc.
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WORLDWIDE SALES AND SERVICE
AMERICAS
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01/05/10
DS22242A-page 88
2010 Microchip Technology Inc.

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